mc68hc11g5 Freescale Semiconductor, Inc, mc68hc11g5 Datasheet
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... Freescale Semiconductor, Inc MC68HC11G5 MC68HC11G7 MC68HC711G5 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com MC68HC11G5/D 1 ...
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... Freescale Semiconductor, Inc. MC68HC11G5 MC68HC11G7 MC68HC711G5 High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller For More Information On This Product, Go to: www.freescale.com Unit ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number TABLE OF CONTENTS Paragraph Number 1.1 General ........................................................................................................ 1.2 Features of the Freescale MC68HC11G5 MCU ............................................ Operating Modes and Signal Description 2.1 Operating Modes ......................................................................................... 2.1.1 Single Chip Operating Mode .................................................................. 2.1.2 Expanded Non-Multiplexed Operating Mode ......................................... 2.1.3 Bootstrap Operating Mode ..................................................................... 2.1.4 Test Operating Mode .............................................................................. 2.1.4.1 Factory Test Register (TEST1) ......................................................... ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Memory and Control/Status Registers 3.1 ROM ............................................................................................................. 3.2 Bootstrap ROM ............................................................................................ 3.3 RAM ............................................................................................................. 3.4 Memory Map ................................................................................................ 3.4.1 Single Chip Mode ................................................................................... 3.4.2 Expanded Non-multiplexed Mode .......................................................... 3.4.3 Special Bootstrap Mode ......................................................................... 3.4.4 Special Test Mode .................................................................................. 3.4.5 Changing Modes .................................................................................... 3.5 System Configuration ................................................................................... 3.5.1 RAM and I/O Mapping Register (INIT) ................................................... 3.5.2 Configuration Control Register (CONFIG) .............................................. ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 4.10 Port G ........................................................................................................... 4.10.1 Data Register (PORTG) ......................................................................... 4.10.2 Data Direction Register (DDRG) ............................................................ 4.11 Port H ........................................................................................................... 4.11.1 Data Register (PORTH) ......................................................................... 4.11.2 Data Direction Register (DDRH) ............................................................ 4.12 Port J ............................................................................................................ 4.12.1 Data Register (PORTJ) ......................................................................... 4.12.2 Data Direction Register (DDRJ) ............................................................ 4.13 Expanded Bus (Ports ...................................................................... 4.13.1 R/W ........................................................................................................ 4.13.2 Memory Ready (MRDY) ......................................................................... 4.13.3 Options Register 2 (OPT2) ..................................................................... ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Programmable Timer, Real Time Interrupt and Pulse Accumulator 6.1 Programmable Timer ................................................................................... 6.1.1 Counters ................................................................................................. 6.1.2 Prescalers .............................................................................................. 6.1.3 Input Capture Functions ......................................................................... 6.1.4 Output Compare Functions .................................................................... 6.1.5 Programmable Input Capture/Output Compares .................................... 6.2 Real Time Interrupt ...................................................................................... 6.3 Pulse Accumulator ....................................................................................... 6.4 Timer, RTI and Pulse Accumulator Registers .............................................. ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Serial Communications Interface 7.1 Overview and Features ................................................................................ 7.1.1 SCI Two-wire System Features: ............................................................. 7.1.2 SCI Receiver Features ........................................................................... 7.1.3 SCI Transmitter Features ....................................................................... 7.2 Functional Description ................................................................................. 7.3 Data Format ................................................................................................. 7.4 Receiver Wake-up Operation ....................................................................... 7.4.1 Idle Line Wake-up .................................................................................. 7.4.2 Address Mark Wake-up .......................................................................... 7.5 Receive Data (RXD) ..................................................................................... ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Analog-to-Digital Converter 9.1 Conversion Process ..................................................................................... 9.2 Channel Assignments .................................................................................. 9.3 Single Channel Operation ............................................................................ 9.3.1 4-Conversion, Single Scan ..................................................................... 9.3.2 4-Conversion, Continuous Scan ............................................................. 9.3.3 8-Conversion, Single Scan ..................................................................... 9.3.4 8-Conversion, Continuous Scan ............................................................. 9.4 Multiple Channel Operation ......................................................................... 9.4.1 4-Channel Single Scan ........................................................................... 9.4.2 4-Channel Continuous Scan .................................................................. 9.4.3 8-Channel Single Scan ........................................................................... ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 11.1 Introduction .................................................................................................. 11.2 Mode 0: 8-bit PWM with Selectable Phase Shift .......................................... 11.2.1 Operation of PWM and PA Unit in Mode 0 ............................................. 11.2.2 Register Functions in Mode 0 ................................................................. 11.2.2.1 Counter 1 (EVCNT1) ........................................................................ 11.2.2.2 Compare Register 1A (ECMP1A); (Y) .............................................. 11.2.2.3 Compare Register 1B (ECMP1B); (X’) ............................................. 11.2.2.4 Counter 2 (EVCNT2) ........................................................................ 11.2.2.5 Compare Register 2A (ECMP2A); (X) .............................................. 11.2.2.6 Compare Register 2B (ECMP2B) ..................................................... ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 11.5 Mode 3: 8-bit PWM with 256 Clock Prescaler .............................................. 11.5.1 Operation of Pulse Width Modulation Unit in Mode 3 ............................. 11.5.2 Operation of Pulse Accumulator Unit in Mode 3 .................................... 11.5.3 Register Functions in Mode 3 ................................................................. 11.5.3.1 Counter 1 (EVCNT1) ........................................................................ 11.5.3.2 Compare Register 1A (ECMP1A) ..................................................... 11.5.3.3 Compare Register 1B (ECMP1B) ..................................................... 11.5.3.4 Counter 2 (EVCNT2) ........................................................................ 11.5.3.5 Compare Register 2A (ECMP2A) ..................................................... ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 12.3 Instruction Set .............................................................................................. 12.3.1 Accumulator and Memory Instructions ................................................... 12.3.1.1 Loads, Stores and Transfers ............................................................ 12.3.1.2 Arithmetic Operations ....................................................................... 12.3.1.3 Multiply and Divide ............................................................................ 12.3.1.4 Logical Operations ............................................................................ 12.3.1.5 Data Testing and Bit Manipulation .................................................... 12.3.1.6 Shifts and Rotates ............................................................................ 12.3.2 Stack and Index Register Instructions .................................................... 12.3.3 Condition Code Register Instructions ..................................................... ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Concluded) TABLE OF CONTENTS (Continued) Paragraph Paragraph Number Number MC68HC11G7 High-performance MCU with 24 kbyte ROM MC68HC711G5 High-performance MCU with 16 kbyte EPROM x For More Information On This Product, Go to: www.freescale.com Title Title Appendix A Appendix B Page Page Number Number ...
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... Freescale Semiconductor, Inc. LIST OF TABLES (Continued) LIST OF ILLUSTRATIONS Paragraph Number Number 1-1 Functional Block Diagram ............................................................................ 2-1 Oscillator circuits: (a) External oscillator connections .................................. 2-1 Oscillator circuits: (b) One crystal driving two MCUs ................................... 2-1 Oscillator circuits: (c) Common crystal connections .................................... 3-1 Memory Map ................................................................................................ 3-2 Control and Status Registers (Page 1) ........................................................ 3-2 Control and Status Registers (Page 2) ........................................................ ...
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... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Concluded) Paragraph Number 13-1 Test Methods ............................................................................................... 13-2 Run IDD vs Bus Frequency (Single Chip Mode – 4.5V, 5.5V) ..................... 13-3 Run IDD vs Bus Frequency (Expanded Mode – 4.5V, 5.5V) ....................... 13-4 Wait IDD vs Bus Frequency (Single Chip Mode – 4.5V, 5.5V) .................... 13-5 Wait IDD vs Bus Frequency (Expanded Mode – 4.5V, 5.5V) ...................... ...
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... Freescale Semiconductor, Inc. LIST OF TABLES (Continued) LIST OF TABLES Paragraph Number Number 2-1 Mode Select Summary ................................................................................. 2-2 Bootstrap Mode Jump Vectors ..................................................................... 2-3 Port Signal Functions: (a) Expanded Non-multiplexed and Test Modes ..... 2-3 Port Signal Functions: (b) Single Chip and Bootstrap Modes ...................... 5-1 COP Timeout Periods .................................................................................. 5-2 Interrupt Vector Masks and Assignments .................................................... ...
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... Freescale Semiconductor, Inc. This page intentionally left blank xiv For More Information On This Product, Go to: www.freescale.com ...
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... MC68HC11G5 also includes a real time interrupt circuit and a Computer Operating Properly (COP) watchdog system the original MC68HC11A8. The MC68HC11G7, which is similar to the MC68HC11G5 but with 24 kilobytes of ROM instead of 16 kilobytes, is described in Appendix A. The MC68HC711G5, again similar to the MC68HC11G5 but with 16 kilobytes of EPROM instead of ROM, is described in Appendix B ...
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... Freescale Semiconductor, Inc. • Expanded non-multiplexed data/address buses give access to a total address space of 64 kilobytes • Maximum of seven 8-bit, one 6-bit and one 4-bit I/O ports • 2 separate 16-bit timers, each with its own E-clock divider circuitry • External clock option on Timer 2 • ...
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... OPERATING MODES During reset the MC68HC11G5 uses two mode select pins, MODA and MODB, to select one of two normal modes or one of two special operating modes. The normal operating modes are the single chip mode, which allows maximum use of the pins for on-chip peripheral functions, and the expanded non-multiplexed mode which allows access to the 64 kbytes of memory space including the internal RAM, ROM (if present), and register spaces ...
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... ROM, uses the SCI to read a variable length program into on-chip RAM. Program control is passed to RAM at location $0000 when an idle line of at least four characters occurs. The MC68HC11G5 communicates through the SCI port. After reset in bootstrap mode, the SCI runs at E/16 (7812 baud for E-clock = 2 MHz). A break condition is output on the SCI transmitter. For normal use of the bootstrap program, the user must send $FF to the SCI receiver at either E/16 or E/104 (1200 baud for E-clock = 2 MHz) ...
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... Freescale Semiconductor, Inc. Table 2-2. Bootstrap Mode Jump Vectors Address Pseudo-vector 00B5 Event 2 00B8 Event 1 00BB Timer Overflow 2 00BE Timer Output Compare 7 / Input Capture 00C1 Timer Output Compare 6 / Input Capture 00C4 SCI 00C7 SPI 00CA Pulse Accumulator Input Edge 00CD Pulse Accumulator Overflow ...
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... Freescale Semiconductor, Inc. 2.1.4.1 Factory Test Register (TEST1 $103E TILOP TPWSL OCCR CBYP1 DISR RESET READ: Any time (always zero if not in a test mode) WRITE: Only while SMOD = 1 (TEST or BOOT modes) TILOP — Test Illegal Opcode 0 – Normal operation (trap on illegal opcodes) 1 – ...
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... The DISR control bit has priority over the FCM and FCOP control bits such that, if DISR is set to one, no reset results even when FCM or FCOP is set to one. 2.2 SIGNAL DESCRIPTION The following table shows the pin usage for the MC68HC11G5. 5 Volt Supply ( ...
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... Freescale Semiconductor, Inc. 2.2.2 Reset (RESET) This active low bidirectional control signal pin is used as an input to initialize the MC68HC11G5 to a known start-up state, and as an open-drain output to indicate an internal computer operating properly (COP) watchdog circuit or clock monitor failure. This reset signal is significantly different from the reset signal used on other Freescale MCUs ...
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... Non-Maskable Interrupt (XIRQ) The XIRQ pin provides the capability for applying asynchronous non-maskable interrupts, after reset initialization, to the MC68HC11G5. During reset, the X-bit in the condition code register is set and any interrupt is masked until the MCU software enables it. The XIRQ input is level sensitive, and requires an external pull-up resistor ...
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... Freescale Semiconductor, Inc. 2.2.9 Mode A/Load Instruction Register (MODA/LIR) and Mode B/Standby Voltage (MODB/V ) kam During reset, MODA and MODB are used to select one of the four basic operating modes. Refer to Table 2-1 for mode selection and to paragraph 2.1: OPERATING MODES for additional details. After the operating mode has been selected, the open drain LIR pin goes to an active low level during the first E-clock cycle of each instruction ...
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... Freescale Semiconductor, Inc. Table 2-3. Port Signal Functions: (a) Expanded Non-multiplexed and Test Modes Bit PA0/IC3 PA1/IC2 PA2/IC1 A10 D2 3 PA3/IC4/OC5 (and/or OC1) A11 D3 4 PA4/OC4 (and/or OC1) A12 D4 A13 D5 5 PA5/OC3 (and/or OC1) 6 PA6/OC2 (and/or OC1) A14 D6 7 PA7/PA1 (and/or OC1) ...
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... Freescale Semiconductor, Inc. This page intentionally left blank OPERATING MODES AND SIGNAL DESCRIPTION 2-10 For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. MEMORY AND CONTROL/STATUS REGISTERS This section describes the memory, memory subsystems mapping, and the mapping of the control and status registers of the MC68HC11G5 MCU. 3.1 ROM The internal 16 kilobytes of ROM occupy the highest 16k addresses in the memory map ($C000 – ...
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... MEMORY MAP Each of the normal and special operating modes of the MC68HC11G5 has a default initial memory map. In addition, there is a control register (CONFIG) which can be used to remove (disable) the ROM from the memory map. After reset the INIT register (which is reset to $01 independent of mode and may only be written under specific circumstances) can alter the mapping of RAM and internal I/O resources under software control ...
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... Freescale Semiconductor, Inc. $0000 External $1000 $2000 $3000 $4000 $5000 $6000 External $7000 $8000 $9000 $A000 $B000 $C000 $D000 $E000 $F000 $FFFF Single Expanded Bootstrap Chip Non-Multiplexed Normal Modes Figure 3-1. Memory Map 3.4.2 Expanded Non-multiplexed Mode This normal operating mode is established by having a logic one level on both the MODB/V and the MODA/LIR pin at the rising edge of RESET ...
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... SMOD cannot be written back after being written because the part will no longer special mode. 3.5 SYSTEM CONFIGURATION The MC68HC11G5 allows the user to configure the MCU system to his specific requirements via hard wired options, such as the mode select pins, and via internal software programmable control MEMORY AND CONTROL/STATUS REGISTERS 3-4 For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. registers. Two special internal registers (INIT and CONFIG) require further explanation. The INIT control register allows the RAM and internal register block to be repositioned in the memory map during software initialization. The CONFIG control register controls the presence of ROM in the memory map as well as the NOCOP watch-dog system enable ...
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... Freescale Semiconductor, Inc. Note: There are unused register locations in the 128 byte control and status register block. Reads of these unused registers return data from the undriven internal data bus, not from another source that happens to be located at the same address. 3.5.2 Configuration Control Register (CONFIG) The CONFIG control register is used for system configuration control functions including removal of ROM from the memory map, and enabling of the COP watch-dog system ...
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... Freescale Semiconductor, Inc. $1000 PA7 PA6 PA5 PA4 PA3 $1001 DDA7 DDA6 DDA5 DDA4 DDA3 $1002 PG7 PG6 PG5 PG4 PG3 $1003 DDG7 DDG6 DDG5 DDG4 DDG3 $1004 PB7 PB6 PB5 PB4 PB3 $1005 PF7 PF6 PF5 PF4 PF3 $1006 PC7 ...
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... Freescale Semiconductor, Inc. $1020 OM2 OL2 OM3 OL3 OM4 $1021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A TCTL2 $1022 OC1I OC2I OC3I OC4I 4/5I $1023 OC1F OC2F OC3F OC4F 4/5F $1024 TO1I RTII PAOVI PAII TO2I $1025 TO1F RTIF PAOVF PAIF TO2F ...
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... Freescale Semiconductor, Inc. $1040 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 $1041 Bit 7 Bit $1042 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 $1043 Bit 7 Bit $1044 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 $1045 Bit 7 Bit $1046 Bit 15 Bit 14 Bit 13 Bit 12 ...
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... Freescale Semiconductor, Inc. $1060 CON34 CON12 PCKA2 PCKA1 0 $1061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 $1062 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PWEN4 PWEN3 PWEN2 PWEN1 $1063 $1064 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 $1065 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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... Freescale Semiconductor, Inc. INPUT/OUTPUT PORTS There are seven 8-bit I/O ports, one 6-bit I/O port and one 4-bit I/O port on the MC68HC11G5. Most of the 66 I/O pins serve multiple purposes depending on the configuration of the MCU system (see Table 2-3). The configuration is controlled in turn, by hardware mode selection as well as by several internal control registers ...
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... Freescale Semiconductor, Inc. preserve the Port functions that are displaced by the expanded modes, these functions become externally accessible functions so that they may be emulated with external hardware, if required. The internal register addresses that become external accesses are PORTB, DDRC, PORTC and PORTF. ...
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... Freescale Semiconductor, Inc. controlled by the DDRA bits whether IC3, IC2, and IC1 are enabled or not. Port A bits 3 – 7 are controlled by the DDRA bits only when the associated output compare functions are disabled. Enabling an output compare function forces the corresponding port bit output, irrespective of the state of the DDRA bit ...
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... Freescale Semiconductor, Inc. Note: The timer forces each Port A line associated with an enabled output compare output. In such cases the data direction bits will not be changed but will have no effect on these lines. DDRA will revert to controlling the I/O state of a pin when the associated timer output compare is disabled ...
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... Freescale Semiconductor, Inc. In the single chip modes (normal and bootstrap), the Port C pins are general purpose I/O pins. Bits 0 – 7 are input or output pins depending on the corresponding bit of DDRC. While a bit is configured as an output, reading the bit returns the sensed level at the input to the Port C pin driver. At reset, all DDRC bits are cleared and all Port C bits are configured as inputs ...
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... Freescale Semiconductor, Inc. Port D bit 1 becomes the Transmit Data output (TXD) when the SCI transmitter is enabled (TE bit in the SCCR2 register set to one). When the TE bit is clear, Port D bit 1 defaults to being a general purpose I/O pin controlled by DDRD. Note that the transmit logic will retain control of Port D bit 1 after TE is cleared until all transmit operations have finished, including completion of transmission of data from the serial shifter, a queued idle, or queued break ...
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... Freescale Semiconductor, Inc. RESET: $00 (all general purpose I/O configured for input only). 0 – Bits set to zero configure the corresponding I/O pins as inputs. 1 – Bits set to one configure the corresponding I/O pins as outputs. Bit 5 of Port D is dedicated as the active low slave select (SS) input, when the SPI system is enabled. ...
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... Freescale Semiconductor, Inc. 4.9 PORT F Port 8-bit general purpose output port which also supports the external address bus. In the expanded modes (normal expanded and test), these pins act as the low order address output pins. During each MCU cycle, bits 0 – the address are driven out of bits 0 – Port F. When the NHALT bit in the OPT2 register is cleared and the HALT input is pulled low, all output buffers on Port F pins go tri-state ...
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... Freescale Semiconductor, Inc. 4.10.1 Data Register (PORTG $1002 PG7 PG6 PG5 RESET READ: Any time (inputs return pin levels; outputs return pin driver input levels). WRITE: Data stored in an internal latch (drives pins only if configured as outputs). RESET: General purpose high impedance inputs ($00) 4 ...
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... Freescale Semiconductor, Inc. Bit 6 of Port H is used as the event output (EVO general purpose I/O. When the EVOEN bit in the EVCTL register is set, bit 6 of Port H becomes EVO regardless of the state of DDRH bit 6. This does not change the state of DDRH bit 6. When the EVOEN bit in the EVCTL register is cleared, the data direction of the pin is under the control of DDRH bit 6 ...
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... Freescale Semiconductor, Inc. 4.12 PORT J Port general purpose 4-bit I/O port which also supports some of the timer functions (see SECTION 6: PROGRAMMABLE TIMER, REAL TIME INTERRUPT AND PULSE ACCUMULATOR). Two of the pins are used for input capture/output compare. One of the pins is used as a clock input for the timer counter registers. The one remaining pin is for general purpose I/O ...
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... The registers which become external accesses are PORTC, DDRC, PORTB and PORTF. 4.13.1 R/W The read/write output signal (R/ dedicated function when the MC68HC11G5 is in normal expanded mode or test mode. The timing of this signal is the same as the timing for a Port B address output, except for the hold time from the falling edge of E, which is extended so that no special circuitry is needed in a multi-board expanded system ...
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... Freescale Semiconductor, Inc. 4.13.2 Memory Ready (MRDY) A memory ready function is available on the MC68HC11G5. This allows interfacing to slow peripherals and dual ported RAM, and to dynamic RAM without a hidden refresh. When the memory ready function is enabled, MRDY is used to stretch the CPU timing and E-clock to allow a longer access time ...
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... Freescale Semiconductor, Inc. IRV — Internal Read Visibility READ: Any time. WRITE: If SMOD=1, any time. If SMOD=0, only one write is allowed. RESET: Test and bootstrap modes – 1; single chip and expanded modes – – No visibility of internal reads on external bus. 1 – Data from internal reads is driven out on the external data bus. ...
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... Freescale Semiconductor, Inc. RESETS, INTERRUPTS AND LOW POWER MODES This section describes the internal and external resets and interrupts of the MC68HC11G5 and its two low power consumption modes. 5.1 RESETS The MCU can be reset in four ways active-low input to the RESET pin 2 ...
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... Freescale Semiconductor, Inc. 5.1.3 Computer Operating Properly (COP) Reset The MCU contains a watchdog timer which automatically times out unless it is reset within a specific time by a program reset sequence. If the COP watchdog timer is allowed to timeout, a reset is generated which drives the RESET pin low to reset the MCU and the external system. ...
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... Freescale Semiconductor, Inc. Special considerations are needed when using STOP and the clock monitor in the same system. Since the STOP function causes the clocks to be halted, the clock monitor function will generate a reset sequence enabled prior to the STOP mode being entered. For systems which do not expect or want a STOP function, this interaction can be useful to detect the unauthorized execution of a STOP instruction which could not be detected by the COP watchdog system ...
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... CCR, which are set so that interrupt requests will be masked, and the S bit, also in the CCR, which is set so that the STOP instruction is disabled. Memory Map — Immediately after reset the internal memory map of the MC68HC11G5 has 16 kilobytes of ROM located at the top of memory from $C000 – $FFFF (except in expanded mode where the ROM is disabled and these bytes are external accesses), 512 bytes of RAM located at the bottom of memory ($0000 – ...
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... Freescale Semiconductor, Inc. mode). Port C is initialized as an input port (DDRC = $00). Ports B and F are general purpose output ports with all bits initialized to zero. R/W outputs a logic high level all the time. Ports and J are configured as general purpose high-impedance inputs. Port E pins are configured as inputs. ...
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... OPT2 register is initialized to zero in normal modes to protect the system from potential bus conflict with the external system. IRV is initialized to one if the MC68HC11G5 is reset in a special mode (SMOD = 1) to enable internal read visibility for test and debug purposes. The IRQ pin is configured for level sensitive operation (for wired-OR systems) ...
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... Freescale Semiconductor, Inc. Table 5-2. Interrupt Vector Masks and Assignments Vector Address Interrupt Source FFC0, FFC1 Reserved * * * * FFCA, FFCB Reserved FFCC, FFCD Event 2 Event 1 FFCE, FFCF FFD0, FFD1 Timer Overflow 2 FFD2, FFD3 Timer OC7/IC6 FFD4, FFD5 Timer OC6/IC5 FFD6, FFD7 SCI Serial System ...
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... Illegal Opcode Trap Since not all possible opcodes or opcode sequences are defined, an illegal opcode detection circuit has been included in the MC68HC11G5. When an illegal opcode is detected, an interrupt is requested to the illegal opcode vector non-maskable and the illegal opcode vector should never be left uninitialized. ...
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... Freescale Semiconductor, Inc. 5.2.5 Interrupt Mask Bits in Condition Code Register On reset, both the X bit and the I bit in the CCR are set to inhibit all maskable interrupts and XIRQ. After minimum system initialization, software may clear the X bit by a TAP instruction, thus enabling XIRQ interrupts. Thereafter, software cannot set the X bit. Thus, an XIRQ is effectively a non- maskable interrupt ...
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... X and I bits in the condition code register act as class inhibit masks to inhibit all sources in the X bit and/or I bit class. Figures 5-2, 5-3 and 5-4 summarize the priority structure and additional mask conditions that lead to the recognition of interrupt requests in the MC68HC11G5. HIGHEST POWER-ON RESET ...
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... Freescale Semiconductor, Inc BIT YES IN CCR SET ? NO ANY I BIT INTERRUPT PENDING ? NO FETCH OPCODE NO LEGAL STACK CPU OPCODE REGISTERS ? SET X AND I BITS YES FETCH VECTOR $FFF8, FFF9 WAI ? NO YES STACK CPU SWI ? REGISTERS SET X AND I BITS NO FETCH VECTOR $FFF6, FFF7 YES ...
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... Freescale Semiconductor, Inc. BEGIN X BIT YES IN CCR SET ? NO HIGHEST YES PRIORITY INTERRUPT ? NO YES IRQ ? NO YES RTII = YES IC1I = YES IC2I = YES IC3I = YES OC1I = YES OC2I = YES OC3I = YES OC4I = Figure 5-3. Interrupt Priority Resolution ...
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... Freescale Semiconductor, Inc. 2A YES YES TIMER 4/ 4/ YES YES TIMER 5/ 5/ YES YES TIMER 6/ 6/ YES YES TIMER TO1I = 1 ? TO1F ? NO NO YES YES TIMER TO2I = 1 ? TO2F ? NO NO PULSE YES YES ACCUMULATOR PAOVI = 1 ? PAOVF ? NO NO PULSE YES YES ACCUMULATOR PAII = 1 ? PAIF ? NO NO ...
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... Freescale Semiconductor, Inc. BEGIN YES RDRF = YES RIE = YES TDRE = 1 ? TIE = YES TCIE = YES IDLE = 1 ? ILIE = VALID SCI REQUEST Figure 5-4. Interrupt Source Resolution within SCI RESETS, INTERRUPTS AND LOW POWER MODES 5-14 For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. 5.2.7 “Highest Priority I” Interrupt and Miscellaneous Register (HPRIO $103C RBOOT SMOD MDA RESET: — — — RBOOT — Read Bootstrap ROM READ: Any time. WRITE: Only while SMOD = 1 (test or bootstrap modes). RESET: Set in Bootstrap mode, cleared in all other modes. ...
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... Freescale Semiconductor, Inc. PSEL4, PSEL3, PSEL2, PSEL1, PSEL0 — Priority Select bits 4 – 0 READ: Any time. WRITE: Only while I bit in CCR is set (interrupts inhibited). These five bits are used to specify one I bit related interrupt source which will become the highest priority I bit related source (see Table 5-4). ...
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... RAM is retained as long as VDD power is maintained. The CPU state and I/O pin levels are static and are unchanged by the STOP mode. Therefore, when an interrupt comes to restart the system, the MC68HC11G5 resumes processing as if there were no interruption. If reset is used to restart the system a normal reset sequence results where all I/O pins and functions are also restored to their initial states ...
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... Freescale Semiconductor, Inc. sequence leading to normal service of the XIRQ request set to one (XIRQ masked or inhibited), then processing will continue with the instruction which immediately follows the STOP instruction, and no XIRQ interrupt service will be requested or pending. Since the oscillator is stopped in STOP mode, a restart delay may be imposed to allow oscillator stabilization upon leaving the STOP mode. If the internal oscillator is being used, this delay is required ...
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... PROGRAMMABLE TIMER The timer system on the MC68HC11G5 has been derived from the original MC68HC11A8 timer. There are four fixed output compares (OC), three fixed input captures (IC) and three programmable input captures/output compares (IC/OC). Secondly, there are two separate “time-of-day” type 16-bit free-running counters, each with its own prescaler ...
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... Each prescaler is a 3-stage divider with the E-clock as its input, and each stage divides by two. The prescaler output is selectable as E, E/2, E/4, or E/8. After reset, the MC68HC11G5 is configured to use the E-clock as the input to both counters. Initialization software may optionally reconfigure counter 1 to use one of the three prescale taps so that the E-clock is divided before driving the free running counter ...
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... Freescale Semiconductor, Inc. Unlike the other output compare functions, OC1 can automatically affect any or all of the Port A output pins associated with OC2 – OC5 (with OC5/IC4 configured for output compare result of a successful compare between the OC1 register and the 16-bit free running counter. Two 5-bit registers are used in conjunction with this function, the output compare 1 mask register (OC1M) and the output compare 1 data register (OC1D) ...
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... REAL TIME INTERRUPT The real time interrupt feature on the MC68HC11G5 is configured and controlled using three bits (RTR2, RTR1 and RTR0) in the PACTL register to select one of eight interrupt rates. The RTII bit in the TMSK2 register enables the interrupt capability. Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is generated ...
Page 75
... Freescale Semiconductor, Inc. 6.4 TIMER, RTI AND PULSE ACCUMULATOR REGISTERS 6.4.1 Count Registers (TCNT1 and TCNT2 $100E BIT15 BIT14 BIT13 $100F BIT7 BIT6 BIT5 RESET READ: Any time. WRITE: Has no effect for SMOD = 0; forces to $FFF8 for SMOD = 1. RESET: $0000. ...
Page 76
... Freescale Semiconductor, Inc. the counter to be preset to $FFF8 regardless of the data written. This preset capability is intended only for factory testing. Because its width is 16 bits, the value in the free running counter repeats every 65,536 counts (prescaler timeouts). When the count changes from $FFFF to $0000 the timer overflow flag bit (TOxF), in the TFLG2 register, is set ...
Page 77
... Freescale Semiconductor, Inc. PR2B, PR2A — Timer Prescaler Select These bits specify the number of divide-by-2 stages to be inserted between the E-clock and timer counter 2. Note: these bits have no effect if the external clock is selected (TEDGB or TEDGA = 1). PR2B PR2A PR1B, PR1A — Timer Prescaler select These bits specify the number of divide-by-2 stages to be inserted between the E-clock and timer counter 1 ...
Page 78
... Freescale Semiconductor, Inc. READ: Any time. WRITE: Has no meaning or effect. RESET: Indeterminate (not initialized). These registers are used to latch the value of timer counter 2 when a defined transition is sensed by the corresponding input capture edge detector. The result obtained by an input capture corresponds to the value of the counter one cycle after the transition which triggered the edge detection logic ...
Page 79
... Freescale Semiconductor, Inc. 6.4.5 Output Compare 5/Input Capture 4 Register (TO5I4) This is a shared register which acts as the output compare OC5 register or as the input capture IC4 register depending on the state of the I4/O5 bit in the PACTL register. This register is associated with timer counter 1 and with Port A, bit 3. ...
Page 80
... Freescale Semiconductor, Inc. 6.4.7 Output Compare 7/Input Capture 6 Register (TO7I6) This is a shared register which acts as the output compare OC7 register or as the input capture IC6 register depending on the state of the I6/O7 bit in the TCTL4 register. This register is associated with timer counter 2 and with Port J, bit 2. ...
Page 81
... Freescale Semiconductor, Inc. 6.4.9 Output Compare 1 Action Data Register (OC1D $100D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 RESET READ: Any time (bits 2 – 0 always return 0). WRITE: Any time (writes to bits 2 – 0 have no meaning or effect). RESET: $00 OC1D is used to specify the data to be written to the affected bits of Port A as the result of a successful OC1 compare. The bits of OC1D correspond bit-for-bit with the bits of Port A (bits 3 – ...
Page 82
... Freescale Semiconductor, Inc. 6.4.11 Control Register 1 (TCTL1 $1020 OM2 OL2 OM3 RESET READ: Any time. WRITE: Any time. RESET: $00 OMx — Output Mode; OLx — Output Level These four pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare (OC2 – ...
Page 83
... Freescale Semiconductor, Inc. EDGxB EDGxA Note: input captures do not force the direction of the associated port. If the port bit associated with an input capture is programmed output, then input captures will occur on the appropriate changes of state caused by writing to the port. ...
Page 84
... Freescale Semiconductor, Inc. OMx OLx Output compare OC6 only functions if the TO6I5 register is programmed for output compare OC6 operation by the I5/O6 bit in the TCTL4 register being set to zero. Output compare OC7 functions only if the TO7I6 register is programmed for output compare OC7 operation by the I6/O7 bit in the TCTL4 register being set to zero ...
Page 85
... Freescale Semiconductor, Inc. 6.4.15 Main Timer Interrupt Mask Register 1 (TMSK1) The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. A zero disables the corresponding flag from causing a hardware interrupt. A one enables the corresponding flag to cause a hardware interrupt $1022 OC1I ...
Page 86
... Freescale Semiconductor, Inc. OC1F, OC2F,OC3F, OC4F — Output Compare “x” Flag Set when the 16-bit timer counter register matches the OCx compare register. These bits are cleared by writing to the TFLG1 register with the corresponding bits (4–7) set. 4/5F — Input Capture 4/Output Compare 5 Flag Set when an input capture occurs on IC4 or an output compare occurs on OC5 ...
Page 87
... Freescale Semiconductor, Inc. TO2I — Timer Overflow 2 Interrupt Enable 0 – Interrupt inhibited 1 – Hardware interrupt requested when TO2F flag set 5/6I — Input Capture 5/Output Compare 6 Interrupt Enable 0 – Interrupt inhibited 1 – Hardware interrupt requested when 5/6F flag set 6/7I — Input Capture 6/Output Compare 7 Interrupt Enable 0 – ...
Page 88
... Freescale Semiconductor, Inc. PAIF — Pulse Accumulator Input Edge Flag Set when the selected edge is detected at the PAI input pin. In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the PAI input pin triggers PAIF. This bit is cleared by writing to the TFLG2 register with bit 4 set. TO2F — ...
Page 89
... Freescale Semiconductor, Inc. 6.4.20 Pulse Accumulator Control Register (PACTL $1026 0 PAEN PAMOD PEDGE RESET READ: Any time. WRITE: Any time. RESET: $00 PAEN — Pulse Accumulator System Enable When PAEN is zero, the pulse accumulator counter is disabled from counting and the PAIF and PAOVF flags cannot be set. The counter value and the states of the two flags are not altered by the state of the PAEN bit (writing PAEN to zero does not clear them) ...
Page 90
... Freescale Semiconductor, Inc. I4/O5 — Configure TO5I4 register for input capture or output compare 0 – Output compare 5 function enabled (no IC4). 1 – Input capture 4 function enabled (no OC5). RTR2, RTR1, RTR0 — RTI Interrupt Rate These bits select one of six rates for the real time periodic interrupt circuit (see Table 6-1) ...
Page 91
... CRT terminal or personal computer to the MCU or to form a serial communication network connecting several widely distributed MCUs. It should be noted that the SCI is one of two independent serial I/O subsystems in the MC68HC11G5. The other serial I/O system on the MC68HC11G5, the serial peripheral interface (SPI), provides for high speed synchronous serial communication to peripherals or other MCUs (usually located on the same PC board as the MC68HC11G5) ...
Page 92
... Freescale Semiconductor, Inc. • Framing error detect. • Noise detect. • Overrun detect. • Receiver data register full flag. 7.1.3 SCI Transmitter Features • Transmit data register empty flag. • Transmit complete flag. • Send break. 7.2 FUNCTIONAL DESCRIPTION A block diagram of the SCI is shown in Figure 7-1. The user has option bits in serial control register 1 (SCCR1) to select the “ ...
Page 93
... Freescale Semiconductor, Inc. SCI Interrupt Transmit Data Register (See Note) Transmit Data Shift Register TXD (PD1) SCSR IDLE RDRF TC TDRE $102E SBK TE Transmit Flag Control Control Rate Generator $102B TCLR 0 SCP1 SCP0 RCKB SCR2 SCR1 $102C Figure 7-1. Serial Communications Interface Block Diagram Note: The Serial Communications Data Register (SCDAT) is controlled by the internal R/W signal ...
Page 94
... Figure 7-3. Data Format 7.4 RECEIVER WAKE-UP OPERATION The MC68HC11G5 receiver logic hardware also supports a receiver wake-up function which is intended for systems having more than one receiver. With this function a transmitting device directs messages to an individual receiver or group of receivers by passing addressing information as the initial byte(s) of each message ...
Page 95
... Freescale Semiconductor, Inc. The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2 register. While RWU is set, all of the receiver related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot become set). Note that the idle line detect function is inhibited while the RWU bit is set ...
Page 96
... Freescale Semiconductor, Inc. 7.6 START BIT DETECTION When the RXD input is detected low tested for three more sample times (referred to as the start edge verification samples in Figure 7-5 least two of these three verification samples detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A noise flag is set if all three verification samples do not detect a logic zero ...
Page 97
... Freescale Semiconductor, Inc. Data Expected Stop Receive Data In Data Samples (a) Case 1, Receive Line Low During Artificial Edge Data Expected Stop Receive Data In Data Samples (b) Case 2, Receive Line High During Expected Start Edge Figure 7-6. SCI Artificial Start Following a Framing Error Expected Stop ...
Page 98
... Freescale Semiconductor, Inc. 7.7 TRANSMIT DATA (TXD) Transmit data is the serial data from the internal data bus that is applied through the serial communications interface to the output line. The transmitter generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock ...
Page 99
... Freescale Semiconductor, Inc. R8 — Receive Data Bit 8 READ: Any time. WRITE: Has no meaning or effect. This bit is the ninth serial data bit received when the SCI system is configured for nine data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred into this bit at the same time as the remaining eight bits (bits 0 – ...
Page 100
... Freescale Semiconductor, Inc. READ: Any time WRITE: Any time RESET: $00 TIE — Transmit Interrupt Enable 0 – TDRE interrupts disabled 1 – SCI interrupt if TDRE = 1 TCIE — Transmit Complete Interrupt Enable 0 – TC interrupts disabled 1 – SCI interrupt RIE — Receiver Interrupt Enable 0 – ...
Page 101
... Freescale Semiconductor, Inc. of the break code, the transmitter sends at least one high bit to guarantee recognition of a valid start bit. If the transmitter is currently empty and idle, setting and clearing SBK is likely to queue two character times of break because the first break transfers almost immediately to the shift register and the second is then queued into the parallel transmit buffer ...
Page 102
... Freescale Semiconductor, Inc. NF — Noise Error Flag This bit is set if there is noise on a “valid” start bit, any of the data bits the stop bit. The NF bit is set during the same cycle as the RDRF bit but does not get set in the case of an overrun (OR). FE — ...
Page 103
... Freescale Semiconductor, Inc. Table 7-1. First Prescaler Stage SCP1 SCP0 SCR2, SCR1, SCR0 — SCI Rate Select bits READ: Any time WRITE: Any time These three bits select the baud rates for both the transmitter and the receiver. The prescaler output described above is divided by the factors shown in Table 7-2. ...
Page 104
... Freescale Semiconductor, Inc. RCKB — SCI Receive Baud Rate Clock Test READ: Always returns logic 0 WRITE: Only while SMOD = 1 (test or bootstrap mode) This bit is disabled and remains low in any mode other than test or bootstrap modes. Reset clears this bit. While in test or bootstrap mode, this bit may be written but not read (reads always return a logic zero) ...
Page 105
... In a serial peripheral interface, separate wires (signals) are required for data and clock. In the SPI format, the clock is not included in the data stream and must be furnished as a separate signal. The MC68HC11G5 SPI system may be configured either as a master slave. ...
Page 106
... Freescale Semiconductor, Inc. 8.2.1 Master In Slave Out (MISO) The MISO line is configured as an input in a master device and as an output in a slave device one of the two lines that transfer serial data in one direction, with the most significant bit sent first. The MISO line of a slave device is placed in the high-impedance state if the slave is not selected. ...
Page 107
... Freescale Semiconductor, Inc. As shown in Figure 8-1, four different timing relationships may be selected by control bits CPOL and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate with the same timing. The master device always places data on the MOSI line a half cycle before the clock edge (SCK), in order for the slave device to latch the data ...
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... Freescale Semiconductor, Inc. 8.3 FUNCTIONAL DESCRIPTION Internal MCU Clock MSB Divider SPI Clock (Master) Select MSTR SPE SPI Control SPI Status Register SPI Interrupt Request Figure 8-2. Serial Peripheral Interface Block Diagram SERIAL PERIPHERAL INTERFACE 8-4 For More Information On This Product, Go to: www.freescale.com ...
Page 109
... Due to data direction register control of SPI outputs and the Port D wire-OR mode (DWOM) option, the SPI system can be configured in a variety of ways. Systems with a single bidirectional data path rather than separate MISO and MOSI paths can be accommodated. Since MC68HC11G5 slaves can selectively disable their MISO output, a broadcast message protocol is also possible. ...
Page 110
... Freescale Semiconductor, Inc. When the SPE bit is set the Port D bit and 5 pins are dedicated to the SPI function. If the SPI is in master mode and DDRD bit 5 is set, then the Port D bit 5 pin becomes a general purpose output instead of the SS input. ...
Page 111
... Freescale Semiconductor, Inc. 8.4.2 Status Register (SPSR $1029 SPIF WCOL 0 RESET READ: Any time. WRITE: Has no meaning or effect. SPIF — SPI Interrupt Request Flag The serial peripheral data transfer flag bit is set after the eighth SCK cycle in a data transfer and it is cleared by reading the SPSR register (with SPIF set) followed by reading from or writing to the SPI Data Register (SPDAT). WCOL — ...
Page 112
... Freescale Semiconductor, Inc. the master device. At the completion or transmitting a byte of data, the SPIF status bit is set in both the master and slave devices. When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated or an overrun condition will exist ...
Page 113
... The Analog to Digital converter system consists of a single 10-bit successive approximation type converter and a 16-channel multiplexer. Eight of the channels are connected to pins on the MC68HC11G5, four are unused and the remaining four channels are dedicated to internal reference points or test functions. There are eight 10-bit result registers and control logic allows for four or eight consecutive conversions before stopping or for conversions to continue with the newest conversion overwriting the oldest result register ...
Page 114
... Freescale Semiconductor, Inc. 9.1 CONVERSION PROCESS The A/D converter is ratiometric. An input voltage equal input voltage equal to V converts to $0000. An input voltage greater than V rl $FFC0 with no overflow indication. Note that the six least significant bits always read zero. For ratiometric conversions, the source of each analog input should use V be referenced to V ...
Page 115
... Freescale Semiconductor, Inc. Table 9-1. Channel Assignments (continued) CONV8 = 9.3 SINGLE CHANNEL OPERATION Single channel operation is selected by writing a zero to the MULT bit in the A/D control and status register (ADCTL) ...
Page 116
... Freescale Semiconductor, Inc. 9.3.3 8-Conversion, Single Scan The result of the first conversion will be placed in result register ADR1, while the result of the eighth conversion will be placed in result register ADR8. After the eighth conversion is complete all conversion activity is halted until a new conversion command is written to the ADCTL control register. ...
Page 117
... OPERATION IN STOP AND WAIT MODES If a conversion sequence is still in process when the MC68HC11G5 enters the STOP or WAIT mode, the conversion of the current channel is suspended. When the MCU resumes normal operation, that channel is re-sampled and the conversion sequence resumes. As the MCU exits the WAIT mode, the A/D circuits are stable and valid results can be obtained on the first conversion ...
Page 118
... Freescale Semiconductor, Inc. 9.7 REGISTERS 9.7.1 A/D Control and Status Register (ADCTL $1030 CCF CONV8 SCAN RESET: Undefined READ: Any time. WRITE: Any time except writes always clear bit 7. RESET: Indeterminate. CCF — Conversions Complete Flag This flag bit is set automatically after an A/D conversion cycle (four or eight conversions, depending on which conversion mode is selected) ...
Page 119
... Freescale Semiconductor, Inc. 9.7.2 Result Registers (ADR1 – ADR8 $1040 BIT15 BIT14 BIT13 $1041 BIT7 BIT6 0 $1042 BIT15 BIT14 BIT13 $1043 BIT7 BIT6 0 $1044 BIT15 BIT14 BIT13 $1045 BIT7 BIT6 0 $1046 BIT15 BIT14 BIT13 $1047 BIT7 BIT6 0 $1048 BIT15 BIT14 BIT13 ...
Page 120
... Freescale Semiconductor, Inc. This page intentionally left blank ANALOG-TO-DIGITAL CONVERTER 9-8 For More Information On This Product, Go to: www.freescale.com ...
Page 121
... Freescale Semiconductor, Inc. PULSE WIDTH MODULATION TIMER 10.1 GENERAL OVERVIEW The PWM module provides up to four 8-bit pulse width modulated waveforms on the Port H pins. Channel pairs may be concatenated to create 16-bit PWM outputs. Three clock sources (A, B and S) give the PWM a wide range of frequencies. Figure 10-1 shows the block diagram of the PWM module ...
Page 122
... Freescale Semiconductor, Inc. MCU E Clock PCKA1 Select 32 PCKA2 64 128 PCKB1 Clock B Select PCKB2 PCKB3 PCLK3 PCLK4 CNT4 = 8-Bit Compare 8-Bit Compare PWDTY1 = 8-Bit Compare 8-Bit Compare PWPER1 reset reset PWCNT1 PWCNT2 = 8-Bit Compare 8-Bit Compare PWDTY3 = 8-Bit Compare 8-Bit Compare ...
Page 123
... Freescale Semiconductor, Inc. 10.2 CLOCK SELECTION There are three available clocks (A, B and S). Clock A can be software-selected E/4 or E/8. Clock B can be software selected E/2, E/4,..., E/128. The block diagram of Figure 10-1 depicts the three different clocks and how the scaled clock is created. The scaled clock (S) uses clock input and divides it with a reloadable counter. This counter is compared with a user programmable scale value (in the PWSCAL register) ...
Page 124
... Freescale Semiconductor, Inc. 10.4 BOUNDARY CASES The following boundary conditions cause these results: If PWDTYx = $00, PWPERx > $00, PPOLx = 0; If PWDTYx = $00, PWPERx > $00, PPOLx = 1; If PWDTYx = or > PWPERx, PPOLx = 0; If PWDTYx = or > PWPERx, PPOLx = 1; If PWPERx = $00 & PPOLx = 0; If PWPERx = $00 & PPOLx = 1; 10.5 PWM REGISTERS 10 ...
Page 125
... Freescale Semiconductor, Inc. 10.5.2 Period Registers (PWPERX) There is one period register for each channel. The value in this register determines the period of the associated PWM timer channel. In terms of the internal PWM circuitry, this register is connected to a buffer which compares with the counter register directly. The period value in this register is loaded into the buffer when the counter is cleared by the termination of the previous period write to the counter ...
Page 126
... Freescale Semiconductor, Inc. Note: If the duty register is greater than or equal to the value in the period register there will be no duty change in state. In addition, if the duty register is set to $00 the output will always be in the state which would normally be the state changed to at the duty change of state. ...
Page 127
... Freescale Semiconductor, Inc. CON12 — Concatenate channels 1 and 2 1 – Channels 1 and 2 are concatenated to create one 16-bit PWM channel. (Channel 1 becomes the high order byte and channel 2 becomes the low order byte. The channel 2 output is used as the output for this 16-bit PWM (bit 1 of Port H)). ...
Page 128
... Freescale Semiconductor, Inc. 10.5.5 Polarity Select Register (PWPOL) Each channel has a polarity bit (PPOLx) to start the cycle with a high signal or with a low signal. This is shown on the block diagram as a multiplex select of either the Q output or the Q output of the PWM output flip-flop. When one of the bits in the PWPOL register is set, the associated PWM channel output is high at the beginning of the clock cycle, then goes low when the duty count is reached ...
Page 129
... Freescale Semiconductor, Inc. PPOL3 — Pulse Width Channel 3 Polarity 1 – PWM channel 3 output is high at the beginning of the clock cycle, then goes low when the duty count is reached. 0 – PWM channel 3 output is low at the beginning of the clock cycle, then goes high when the duty count is reached. ...
Page 130
... Freescale Semiconductor, Inc. 10.5.7 Enable Register (PWEN) Each timer has an enable bit (PWENx) to start its waveform output. Writing any of these PWENx bits to one causes the associated Port H line to become an output regardless of the state of the associated DDR bit. This does not change the state of the DDR bit and, when PWENx returns to zero, the DDR bit again controls the I/O state ...
Page 131
... Freescale Semiconductor, Inc. EVENT COUNTER 11.1 INTRODUCTION The event counter consists of two distinct functional blocks. One block functions as an 8-bit pulse accumulator unit (PA), the other as an 8-bit pulse width modulation unit (PWM). Each unit has its own 8-bit counter and two 8-bit compare registers. ...
Page 132
... Freescale Semiconductor, Inc. Mode 0: Pulse Accumulator modifies PWM output by adding offset and controlling the clearing of the PWM Mode 1: PA and PWM are completely independent Mode 2: PA Counts the PWM periods (which may be of variable duration and modulation) Mode 4: PA acts as programmable 8-bit prescaler ...
Page 133
... Freescale Semiconductor, Inc. 11.2 MODE 0: 8-BIT PWM WITH SELECTABLE PHASE SHIFT In mode 0, the event counter operates as an 8-bit PWM unit with an 8-bit phase shifter. If mode 0 is selected (EVMDB = 0, EVMDA = 0), then the elements of the event counter are configured as shown in Figure 11-2. EVI2 (PH4) INPUT2 ...
Page 134
... Freescale Semiconductor, Inc. The two counter registers (EVCNT1 and EVCNT2) are clocked by the same signal via the INPUT1 selector. This clock signal can be the E-clock, a scaled E-clock or an external signal applied to the EVI1 pin. If the clock signal is the E-clock or a derivative, an external gating signal can be applied to EVI1 ...
Page 135
... Freescale Semiconductor, Inc. the value Y in ECMP1A, the event output (EVO) will always be low (when EVPOL = 0). Note that this skew value should be a smaller value than the minimum value of the pulse width Y. (If the value in this register is larger than the value Y in ECMP1A possible to miss a pulse in one cycle and the following cycle will be reversed in polarity cycle, which is equivalent to exchanging X’ ...
Page 136
... Freescale Semiconductor, Inc. 11.3 MODE 1: 8-BIT PWM AND PULSE ACCUMULATOR In mode 1, the event counter operates as two independent 8-bit pulse accumulators or as one 8- bit pulse accumulator and one 8-bit PWM. The two counters work independently of each other. If mode 1 is selected (EVMDB = 0, EVMDA = 1), then the elements of the event counter are configured as shown in Figure 11-3 ...
Page 137
... Freescale Semiconductor, Inc. Both units can be driven by the E-clock, a scaled E-clock or by external signals applied to the EVI1 and EVI2 pins. However, note that only one scaled value of the E-clock can be selected. For example, if E/4 is selected as the clock source for EVCNT1, the only E-clock derivatives that can be chosen as the clock source for EVCNT2 are E and E/4 ...
Page 138
... Freescale Semiconductor, Inc. 11.3.3.2 Compare Register 1A (ECMP1A) This compare register holds the value of the PWM period which determines when interrupt 1 (EVENT1) occurs successful comparison with EVCNT1, it generates EVENT1, clears EVCNT1 and resets output EVO to zero (when EVPOL = 0). 11.3.3.3 Compare Register 1B (ECMP1B) This compare register holds the duty value which determines when the output (EVO) is set to one (when EVPOL = 0) ...
Page 139
... Freescale Semiconductor, Inc. 11.3.3.9 Output Unit (EVO) This unit controls the output signal from the PWM unit. If the EVOEN bit in the EVCTL register is set to one, the EVO unit is enabled. The state of the EVPOL bit in the EVCTL register then determines the polarity of the event output. If EVO is not required for pulse width modulation, the EVOEN bit should be reset to zero to disable the EVO unit and to allow pin PH6 to be used for general purpose I/O ...
Page 140
... Freescale Semiconductor, Inc. The only difference between this mode and mode 1 lies in the clock source used to drive the counter in the PA unit (EVCNT2). In mode 1, the clock signal comes via the INPUT1 selector and is either derived from the E-clock (gated or ungated external signal. In mode 2, the signal which results from a successful comparison between EVCNT1 and ECMP1A in the PWM unit is used to drive EVCNT2 in the PA unit ...
Page 141
... Freescale Semiconductor, Inc. 11.4.3.2 Compare Register 1A (ECMP1A) This compare register holds the value of the PWM period which determines when interrupt 1 (EVENT1) occurs successful comparison with EVCNT1, it generates EVENT1, clears EVCNT1, resets output EVO to zero (when EVPOL = 0) and clocks EVCNT2 in the PA unit. ...
Page 142
... Freescale Semiconductor, Inc. 11.5 MODE 3: 8-BIT PWM WITH 256 CLOCK PRESCALER In mode 3, the event counter operates as an 8-bit PWM unit with a software programmable 8-bit clock prescaler (the PA unit). If mode 3 (EVMDB = 1, EVMDA = 1) is selected then the elements of the event counter are configured as shown in Figure 11-5. ...
Page 143
... Freescale Semiconductor, Inc. EVI2 (PH4) E E/2 INPUT2 E/4 E/8 E/16 E/32 E/64 E/128 Figure 11-5. 8-bit PWM with 256 Clock Prescaler (Mode 3) The PWM unit will also work as a pulse accumulator by switching off the output signal to the EVO pin (PH6) and ignoring ECMP1B. 11.5.2 Operation of Pulse Accumulator Unit in Mode 3 The PA unit can be clocked by the E-clock, a scaled E-clock external signal applied to the EVI2 (PH4) pin ...
Page 144
... Freescale Semiconductor, Inc. any 8-bit value to define when the counter is cleared and the PWM clocked. It causes the PA unit to act as a prescaler for the PWM by dividing the clock signal, coming via INPUT2, by any value between 1 and 256. ECMP2B can be used to generate an interrupt signal EVENT2 after a required number of input pulses have been accumulated by EVCNT2 ...
Page 145
... Freescale Semiconductor, Inc. 11.5.3.8 Input Unit 2 (EVI2) This input unit selects the clock source for EVCNT2. If the input signal EVI2 (PH4) is used as a clock source, this unit will select the rising edge or falling edge of the input signal. If the time base counter is used as a clock source, this unit will select the active gate input level which inhibits counting while this input signal is at the active level ...
Page 146
... Freescale Semiconductor, Inc. EVCKC EVCKB EVCKA 11.6.2 Counter Control Register (EVCTL $1071 EVOEN EVPOL EVI2C RESET READ: Any time. WRITE: Any time. RESET: $00. EVOEN — Event Output Enable (Port H, bit 6) 1 – ...
Page 147
... Freescale Semiconductor, Inc. The following table applies to mode 0 only: EVI2C EVI2B EVI2A mode 0, EVI2 is used as a “clear” input to (EVCNT2). Note: In mode 2, these three bits should be reset to zero to allow PH4 to be used as an I/O port. ...
Page 148
... Freescale Semiconductor, Inc. EV2I — Event 2 Interrupt Enable 0 – Interrupt inhibited. 1 – Hardware interrupt requested when EV2F flag set. EV1I — Event 1 Interrupt Enable 0 – Interrupt inhibited. 1 – Hardware interrupt requested when EV1F flag set. 11.6.4 Interrupt Flag Register (EVFLG $1073 ...
Page 149
... Freescale Semiconductor, Inc. 11.6.6 Counter Compare Registers (ECMPx $1076 BIT7 BIT6 BIT5 $1077 BIT7 BIT6 BIT5 $1078 BIT7 BIT6 BIT5 $1079 BIT7 BIT6 BIT5 RESET READ: Any time. WRITE: Any time. RESET: $FF. Compare registers ECMP1A and ECMP1B are associated with counter EVCNT1. Compare registers ECMP2A and ECMP2B are associated with counter EVCNT2 ...
Page 150
... Freescale Semiconductor, Inc. 11.9 BOUNDARY CONDITIONS OF THE PWM FUNCTION The PWM function (In modes 1, 2, and 3) follows the boundary conditions described below. The period is determined by the value in the ECMP1A register (8-bit). The duty value is determined by the values in the ECMP1A and ECMP1B registers (8-bit). ...
Page 151
... Reference Manual (M68HC11RM/D). 12.1 PROGRAMMING MODEL AND CPU REGISTERS In addition to being able to execute all M6800 and M6801 instructions, the MC68HC11G5 uses a 4-page opcode map to allow execution of 91 new opcodes (see 12.3: INSTRUCTION SET). Seven registers, shown in Figure 12-1 and discussed in the following paragraphs, are available to programmers ...
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... Freescale Semiconductor, Inc. 12.1.1 Accumulators A and B Accumulator A and accumulator B are general purpose 8-bit registers used to hold operands and results of arithmetic calculations or data manipulations. These two accumulators can be concatenated into a single 16-bit accumulator called accumulator D. 12.1.2 Index Register X (IX) The 16-bit IX register is used for indexed mode addressing. It provides a 16-bit indexing value which is added to an 8-bit offset provided in an instruction to create an effective address ...
Page 153
... In most applications, this 256-byte area is reserved for frequently referenced data. In the MC68HC11G5, software can configure the memory map so that internal RAM, and/or internal registers or external memory can occupy these addresses ...
Page 154
... For a detailed explanation of each instruction refer to the M68HC11 Reference Manual (M68HC11RM/D). In order to expand the number of instructions used in the MC68HC11G5, a pre-byte mechanism has been added which affects certain instructions. Most of the instructions affected are associated with the Y index register. Instructions which do not require a pre-byte are said to reside in page 1 of the opcode map ...
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... Freescale Semiconductor, Inc. 12.3.1 Accumulator and Memory Instructions Most of these instructions use two operands. One operand is either an accumulator or an index register while the second operand is usually obtained from memory using one of the addressing modes discussed earlier. These accumulator memory instructions can be divided into six subgroups: 1 ...
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... Freescale Semiconductor, Inc. 12.3.1.2 Arithmetic Operations This group of instructions supports arithmetic operations on a variety of operands. 8 and 16-bit operations are supported directly and can easily be extended to support multiple word operands. Twos complement (signed) and binary (unsigned) operations are supported directly. BCD arithmetic is supported by following normal arithmetic instruction sequences with the decimal adjust accumulator A (DAA) instruction to restore results to BCD format ...
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... Freescale Semiconductor, Inc. 12.3.1.3 Multiply and Divide One multiply and two divide instructions are provided. The 8-bit by 8-bit multiply instruction (MUL) produces a 16-bit result. The integer divide (IDIV) performs a 16-bit by 16-bit divide and produces a 16-bit result and a 16-bit remainder. The fractional divide (FDIV) divides a 16-bit numerator by a larger 16-bit denominator to produce a 16-bit result (a binary weighted fraction between 0 and 0 ...
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... Freescale Semiconductor, Inc. 12.3.1.5 Data Testing and Bit Manipulation This group of instructions is used to operate on operands as small as a single bit, but these instructions can also operate on any combination of bits within any 8-bit location in the 64 kbyte memory space. The bit test (BITA or BITB) instructions perform an AND operation within the CPU to update condition code bits without altering either operand ...
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... Freescale Semiconductor, Inc. 12.3.1.6 Shifts and Rotates The shift and rotate functions in the M68HC11 CPU all involve the carry bit in the condition code register in addition to the 8 or 16-bit operand in the instruction. This permits easy extension to multiple word operands. Also, by setting or clearing the carry bit before a shift or rotate instruction, the programmer can easily control what will be shifted into the opened end of an operand ...
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... Freescale Semiconductor, Inc. 12.3.2 Stack and Index Register Instructions The following table summarizes the instructions available for the 16-bit index registers (X and Y) and the 16-bit stack pointer. Table 12-7. Stack And Index Register Instructions Function Mnemonic Add Accumulator Add Accumulator Compare X to Memory (16 Bit) ...
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... Freescale Semiconductor, Inc. the original value of the D accumulator is automatically preserved in the index register while the pointer is being manipulated in the D accumulator. When pointer calculations are finished, another exchange simultaneously updates the index register and restores the D accumulator to its former value. The transfers between an index register and the stack pointer deserve additional comment. The stack pointer always points at the next free location on the stack as opposed to the last thing that was pushed onto the stack ...
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... Freescale Semiconductor, Inc. The XIRQ interrupt mask (X) bit is another unusual case. The definition of this bit specifically states that software shall not be allowed to change X from fact, this is even prohibited by hardware logic. This immediately eliminates a need for a set X instruction. For arguments similar to those used ...
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... Freescale Semiconductor, Inc. Table 12-9. Branches Function Mnemonic Branch if Carry Clea Branch if Carry Set Branch if Equal Zero Branch if Greater Than or Equa Branch if Greater Than Branch if Higher Branch if Higher or Same (same as BCC) Branch if Less Than or Equa Branch if Lower (same as BCS) Branch if Lower or Same ...
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... Freescale Semiconductor, Inc. 12.3.4.2 Jumps The jump instruction allows control to be passed to any address in the 64 kbyte memory map. Table 12-10. Jumps Function Jump 12.3.4.3 Subroutine Calls and Returns (BSR, JSR, RTS) These instructions provide an easy way to break a programming task into manageable blocks called subroutines. The CPU automates the process of remembering the address in the main program where processing should resume after the subroutine is finished ...
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... Freescale Semiconductor, Inc. Wait for interrupt (WAI) has two main purposes. WAI is executed to place the MCU in a reduced power consumption standby state (WAIT mode) until some interrupt occurs. The other use is to reduce the latency time to some important interrupt. The reduction of latency comes about because the time consuming task of storing the CPU registers on the stack is done as soon as the WAI instruction starts to execute ...
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... Freescale Semiconductor, Inc. This page intentionally left blank CPU, ADDRESSING MODES AND INSTRUCTION SET 12-16 For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. ELECTRICAL SPECIFICATIONS This section contains the electrical specifications and associated timing information for the MC68HC11G5. † 13.1 MAXIMUM RATINGS Rating Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range * Current Drain per Pin Excluding V DD and One pin at a time, observing maximum power dissipation limits. ...
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... Freescale Semiconductor, Inc. 13.2 THERMAL CHARACTERISTICS Characteristic Thermal Resistance Plastic 13.3 POWER CONSIDERATIONS The average chip junction temperature, T equation: Where: Ambient temperature ( Package thermal resistance, junction-to-ambient ( o C/ INT I Internal chip power = I DD INT P = Power dissipation on input and output pins (W) — user determined) ...
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... Freescale Semiconductor, Inc. 13.4 DC ELECTRICAL CHARACTERISTICS ( 5.0 Vdc 10 Vdc unless otherwise noted) Characteristic Output Voltage I Load = 10.0 A (See Note 1) All outputs except RESET and MODA Output High Voltage I Load = - 0.8mA 4.5V (See Note 1) Output Low Voltage I Load = 1.6mA ...
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... Freescale Semiconductor, Inc Equivalent Test Load 1 R2 Test PA0-7, PB0-7, PC0-7, PD0, PD5, Point C1 R1 PF0-7, PG0-7, PH0-7, PJ0-3, E, R/W PD1-PD4 V DD Clocks 0.4V Inputs Nominal Timing V DD Outputs V SS D.C. Testing V DD Clocks 20 Inputs Spec Timing V DD Outputs V SS A.C. Testing Notes: 1 ...
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... Freescale Semiconductor, Inc 0.5 1 1.5 0 0.5 1 1.5 Bus Frequency (MHz) Bus Frequency (MHz) Figure 13-2. Run I vs Bus Frequency (Single Chip Mode – 4.5V, 5.5V ...
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... Freescale Semiconductor, Inc 0 0.5 1 Bus Frequency (MHz) Bus Frequency (MHz) Figure 13-4. Wait I vs Bus Frequency (Single Chip Mode – 4.5V, 5.5V 0.5 0 Bus Frequency (MHz) Bus Frequency (MHz) Figure 13-5. Wait I vs Bus Frequency (Expanded Mode – ...
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... Freescale Semiconductor, Inc. 13.5 CONTROL TIMING ( 5.0 Vdc 10 Vdc unless otherwise noted) Characteristic External Oscillator Frequency Internal Operating Frequency Cycle Time Crystal Oscillator Startup Time Stop Recovery Startup Time Wait Recovery Startup Time Reset Input Pulse Width (See Note 1) (To guarantee external reset vector) (Minimum input time ...
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... Freescale Semiconductor, Inc OXOV EXTAL 4064 t cyc E RESET MODA, MODB NEW ADDRESS FFFE FFFE FFFE Figure 13-6. POR External RESET Timing Diagram Internal Clock IRQ (Edge) t ILIH XIRQ, IRQ (Level) E ADDRESS STOP STOP Address + 1 Address (XIRQ (X = 1)) ADDRESS STOP STOP Address + 1 ...
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... Freescale Semiconductor, Inc. E IRQ, XIRQ or Internal Interrupt WAIT WAIT ADDRESS SP SP-1 Addr. Addr+1 R/W Stack Registers Figure 13-8. WAIT Recovery from Interrupt Timing Diagram Last cycle of an instruction E t PCS IRQ (Edge) t ILIH IRQ (Level), XIRQ or Internal Interrupt Next Next ADDRESS SP SP-1 OPCODE OP+1 OP- DATA PCL ...
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... Freescale Semiconductor, Inc. E Internal E External t PCS MRDY ADDRESS DATA Figure 13-10. Memory Ready Timing Diagram LAST INSTRUCTION E LIR HALT ADDRESS OPCODE ADDR DATA OPCODE Figure 13-11. Entering HALT ELECTRICAL SPECIFICATIONS 13-10 For More Information On This Product, Go to: www.freescale.com t PCS OPCODE FETCH HALT STATE t PCS ...
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... Freescale Semiconductor, Inc. HALT STATE EXITING HALT E t PCS LIR HALT ADDRESS DATA Figure 13-12. Exiting HALT ELECTRICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com EXECUTE OPCODE ADDR + 1 t TSD 13-11 ...
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... Freescale Semiconductor, Inc. 13.6 PERIPHERAL PORT CHARACTERISTICS ( 5.0 Vdc 10 Vdc unless otherwise noted) Characteristic Frequency of Operation (E Clock) E Clock Period Peripheral Data Setup Time Port Port E Port G, H Peripheral Data Hold Time Port Port E ...
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... Freescale Semiconductor, Inc. E Clock Ports Port PDSU PDH Port G, H Figure 13-14. Port Read Timing Diagram ELECTRICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com t t PDSU PDH 1/4 t cyc t t PDSU PDH 13-13 ...
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... Freescale Semiconductor, Inc. 13.7 TIMER CHARACTERISTICS ( 5.0 Vdc 10 Vdc unless otherwise noted) Characteristic Timer Pulse Width Input Capture Pulse Accumulator Input Timer Output Compare High Valid Timer Output Compare Low Valid Timer Input Capture Response Delay Min = t cyc + 20ns ...
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... Freescale Semiconductor, Inc. E Clock Value = XXXX Compare Register XXXX - 1 XXXX Counter OC1-OC7 Output OC1-OC7 Output Figure 13-16. Output Compare Timing Diagram E Clock IC1-IC6 IC1-IC6 XXXX - 3 XXXX - 2 Counter Capture Register MAX TCAP Figure 13-17. Input Capture Timing Diagram ELECTRICAL SPECIFICATIONS For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. 13.8 A/D CONVERTER CHARACTERISTICS ( 5.0 Vdc 10 Vdc 750kHz to 2.1MHz unless otherwise noted) Characteristic Parameter Resolution Number of bits resolved by the A/D Nonlinearity Maximum deviation from the ideal A/D transfer characteristics Zero Error Difference between the output of an ideal and an ...
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... Freescale Semiconductor, Inc. 13.9 EXPANSION BUS TIMING ( 5.0 Vdc 10 Vdc unless otherwise noted) Num Characteristic Frequency of Operation (E-Clock) 1 Cycle Time 2 Pulse Width E Low (1/2 t cyc - 23ns) 3 Pulse Width E High (1/2 t cyc - 28ns Rise and Fall Time 9 Address Hold Time ( 1/8 t cyc ...
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... Freescale Semiconductor, Inc. 2 E-Clock 4 12 R/W Address Data (Read) Data (Write) Figure 13-18. Non-multiplexed Expanded Bus ELECTRICAL SPECIFICATIONS 13-18 For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. 13.10 SERIAL PERIPHERAL INTERFACE (SPI) TIMING ( 5.0 Vdc 10 Vdc unless otherwise noted) Num Characteristic Operating Frequency 1 Cycle Time 2 Enable Lead Time 3 Enable Lag Time 4 Clock (SCK) High Time 5 Clock (SCK) Low Time 6 Data Setup Time ...
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... Freescale Semiconductor, Inc held high on Master SS SCK See (CPOL=0) Note SCK See (CPOL=1) Note 6 7 MISO MSB (Input) MOSI MSB (Output) 13 Note: This first edge is generated internally but is not seen at the SCK pin. Figure 13-19. SPI Master Timing (CPHA = held high on Master ...
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... Freescale Semiconductor, Inc SCK (CPOL=0) 2 SCK (CPOL=1) 8 MISO MSB (Output MOSI MSB (Input) Note: Not defined but normally MSB of character just received. Figure 13-21. SPI Slave Timing (CPHA = SCK (CPOL=0) 2 SCK (CPOL= MISO MSB (Output) See Note 6 7 MOSI ...
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... Freescale Semiconductor, Inc. 13.11 EVENT COUNTER CHARACTERISTICS Table 13.1. Clock Input (Required Limit) Clock Input (Required Limit) Num Characteristic 1 Cycle Time of External Clock Input 2 Clock High Time 3 Clock Low Time 4 Rise Time 5 Fall Time Table 13.2. Clock Input (Guaranteed Limit) Clock Input (Guaranteed Limit) ...
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... Freescale Semiconductor, Inc. Table 13.3. Clock Gate Input (Guaranteed Limit) Clock Gate Input (Required Limit) Num Characteristic 1 Gate Input Setup Time to E Fall 2 Gate Input Hold Time to E Fall E Clock Gate Input (EVI1 or EVI2) Figure 13-24. Event Counter Mode – Clock Gate Input Timing Diagram ...
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... Freescale Semiconductor, Inc. This page intentionally left blank ELECTRICAL SPECIFICATIONS 13-24 For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. MECHANICAL DATA This section contains the pin assignments, packaging dimensions and ordering information for the MC68HC11G5 MCU. 14.1 ORDERING INFORMATION Package Type PLCC (CFN Suffix) MECHANICAL DATA For More Information On This Product, Go to: www.freescale.com SECTION 14 Temperature Part Number ...
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... Freescale Semiconductor, Inc. 14.2 PIN ASSIGNMENTS The MC68HC11G5 is offered in an 84-pin PLCC (Quad Surface Mount plastic) package PJ1/OC6/IC5 12 PJ0/TCK 13 PB7/A15 14 PB6/A14 15 PB5/A13 16 PB4/A12 17 PB3/A11 18 PB2/A10 19 PB1/A9 20 PB0/ DDL V 23 SSL PG7 ...
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... Freescale Semiconductor, Inc. 14.3 PACKAGE DIMENSIONS -N- Y BRK D -L- - (Note - — — 0.18 (0.007 — — 0.18 (0.007 0.10 (0.004) J -T- SEATING PLANE G DETAIL S G1 0.25 (0.010 — — ...
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... Freescale Semiconductor, Inc. This page intentionally left blank 14-4 For More Information On This Product, Go to: www.freescale.com MECHANICAL DATA ...
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... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...