mc68hc705jb2 Freescale Semiconductor, Inc, mc68hc705jb2 Datasheet
mc68hc705jb2
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mc68hc705jb2 Summary of contents
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... Freescale Semiconductor, Inc. 68HC705JB2 SPECIFICATION (General Release) August 28, 1998 Consumer Systems Group Semiconductor Products Sector For More Information On This Product, Go to: www.freescale.com HC705JB2GRS/H REV 1.1 ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Section 1.1 FEATURES ...................................................................................................... 1-1 1.2 MASK OPTIONS.............................................................................................. 1-2 1.3 MCU STRUCTURE.......................................................................................... 1-3 1.4 FUNCTIONAL PIN DESCRIPTIONS ............................................................... 1-4 1.4.1 VDD, VSS .................................................................................................... 1-4 1.4.2 OSC1, OSC2 ............................................................................................... 1-4 1.4.3 RESET......................................................................................................... 1-6 1.4.4 IRQ/VPP ...................................................................................................... 1-6 1.4.5 PA0-PA7 ...................................................................................................... 1-7 1.4.6 PB0-PB2 ...................................................................................................... 1-7 1.4.7 D+, D– ......................................................................................................... 1-7 1.4.8 3.3V ............................................................................................................. 1-7 2.1 MEMORY MAP ................................................................................................ 2-1 2.2 I/O AND CONTROL REGISTERS ................................................................... 2-2 2.3 RAM ................................................................................................................. 2-3 2.4 EPROM ............................................................................................................ 2-3 2.5 BOOTLOADER ROM....................................................................................... 2-3 CENTRAL PROCESSING UNIT 3.1 REGISTERS .................................................................................................... 3-1 3.2 ACCUMULATOR (A)........................................................................................ 3-2 3.3 INDEX REGISTER (X) ..................................................................................... 3-2 3.4 STACK POINTER (SP) .................................................................................... 3-2 3 ...
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... Port B Pulldown/Pullup Register.................................................................. 7-5 7.3 I/O PORT PROGRAMMING ............................................................................ 7-6 7.3.1 Pin Data Direction........................................................................................ 7-6 7.3.2 Output Pin.................................................................................................... 7-6 7.3.3 Input Pin....................................................................................................... 7-6 7.3.4 I/O Pin Transitions ....................................................................................... 7-7 7.3.5 I/O Pin Truth Tables..................................................................................... 7-7 ii For More Information On This Product, August 28, 1998 TABLE OF CONTENTS Title SECTION 5 RESETS SECTION 6 LOW POWER MODES SECTION 7 INPUT/OUTPUT PORTS Go to: www.freescale.com Page MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. Section 8.1 TIMER REGISTERS ........................................................................................ 8-2 8.1.1 Timer Counter Register (TCNT) $09 ........................................................... 8-2 8.1.2 Timer Control/Status Register (TCSR) $08 ................................................. 8-3 8.2 OPERATION DURING STOP MODE .............................................................. 8-4 9.1 TIMER REGISTERS (TMRH, TMRL)............................................................... 9-2 9.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL) .................................. 9-3 9.3 INPUT CAPTURE REGISTERS ...................................................................... 9-5 9.4 OUTPUT COMPARE REGISTERS ................................................................. 9-6 9.5 TIMER CONTROL REGISTER (TCR) ............................................................. 9-8 9.6 TIMER STATUS REGISTER (TSR)................................................................. 9-9 9 ...
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... MAXIMUM RATINGS..................................................................................... 13-1 13.2 THERMAL CHARACTERISTICS ................................................................... 13-1 13.3 DC ELECTRICAL CHARACTERISTICS........................................................ 13-2 13.4 USB DC ELECTRICAL CHARACTERISTICS ............................................... 13-3 13.5 USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS............... 13-4 13.6 CONTROL TIMING ........................................................................................ 13-5 13.7 EPROM PROGRAMMING SPECIFICATIONS .............................................. 13-5 iv For More Information On This Product, August 28, 1998 TABLE OF CONTENTS Title SECTION 11 EPROM SECTION 12 INSTRUCTION SET SECTION 13 Go to: www.freescale.com Page MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. Section MECHANICAL SPECIFICATIONS 14.1 20-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) ..................................... 14-1 14.2 20-PIN SURFACE-MOUNT SMALL OUTLINE PACKAGE (SOIC) ............... 14-2 REV 1.1 For More Information On This Product, August 28, 1998 GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS Title SECTION 14 Go to: www.freescale.com Page v ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Section vi For More Information On This Product, August 28, 1998 TABLE OF CONTENTS Title Go to: www.freescale.com Page MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. Figure 1-1 MC68HC705JB2 Block Diagram...................................................................... 1-3 1-2 Pin Assignments for 20-Pin Package............................................................... 1-4 1-3 Oscillator Connections ..................................................................................... 1-5 2-1 MC68HC705JB2 Memory Map ........................................................................ 2-1 2-2 I/O Registers .................................................................................................... 2-2 2-3 I/O Registers $0000-$000F.............................................................................. 2-4 2-4 I/O Registers $0010-$001F.............................................................................. 2-5 2-5 I/O Registers $0020-$003F.............................................................................. 2-6 2-6 Mask Option Register $01FF ........................................................................... 2-6 3-1 MC68HC05 Programming Model ..................................................................... 3-1 4-1 Interrupt Processing Flowchart ........................................................................ 4-3 4-2 External Interrupt (IRQ) Logic .......................................................................... 4-4 4-3 IRQ Control and Status Register (ICSR) ...
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... IN Token Data Flow for Transmit Endpoint 0 ............................................... 10-31 10-32 IN Token Data Flow for Transmit Endpoint 1/ Endpoint 2............................ 10-32 11-1 EPROM Programming Sequence .................................................................. 11-3 14-1 20-Pin PDIP Mechanical Dimensions ............................................................ 14-1 14-2 20-Pin SOIC Mechanical Dimensions ............................................................ 14-2 viii For More Information On This Product, August 28, 1998 LIST OF FIGURES Title Go to: www.freescale.com Page MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. Table 4-1 Reset/Interrupt Vector Addresses .................................................................... 4-2 7-1 Port A I/O Pin Functions................................................................................... 7-7 7-2 Port B I/O Pin Functions................................................................................... 7-7 10-1 Supported Packet Identifiers .......................................................................... 10-5 10-2 Register Summary ....................................................................................... 10-18 11-1 Operation Mode Condition After Reset .......................................................... 11-1 12-1 Register/Memory Instructions ........................................................................ 12-4 12-2 Read-Modify-Write Instructions...................................................................... 12-5 12-3 Jump and Branch Instructions........................................................................ 12-6 12-4 Bit Manipulation Instructions .......................................................................... 12-7 12-5 Control Instructions ........................................................................................ 12-7 12-6 Instruction Set Summary............................................................................... 12-8 12-7 Opcode Map................................................................................................. 12-14 13-1 Maximum Ratings ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table x For More Information On This Product, August 28, 1998 LIST OF TABLES Title Go to: www.freescale.com Page MC68HC705JB2 REV 1.1 ...
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... Customer-Specified Integrated Circuit (CSIC) design strategy. All MCUs in the family use the popular MC68HC05 central processing unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types. The MC68HC705JB2 is specifically designed to be used in applications where a Universal Serial Bus (USB) interface is required. 1.1 FEATURES • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.2 MASK OPTIONS The mask options on the MC68HC705JB2 are handled with five EPROM bits in the Mask Option Register ($01FF). These options are: • External interrupt pins (IRQ, PA0 to PA3): [edge-triggered or edge-and-level-triggered] • Port A and port B pull-down/pull-up resistors: [connected or disconnected] • ...
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... Freescale Semiconductor, Inc. 1.3 MCU STRUCTURE Figure 1-1 shows the block diagram of the MC68HC705JB2. PA0 CPU CONTROL PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 COND CODE REG. 128 Bytes RAM : External edge interrupt capability, with Schmitt trigger input : 8 mA current sink capability ...
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... August 28, 1998 RESET 1 20 VDD PA0 2 19 OSC1 PA1 3 18 OSC2 PA2 VSS 4 17 PA3 5 16 3.3V PA4 PB0/TCAP 7 14 D– PB1 PA7 8 13 PB2 9 12 PA6 IRQ/VPP 10 11 PA5 and GENERAL DESCRIPTION Go to: www.freescale.com . V is the positive supply, DD MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc crystal as shown in Figure 1-3( ceramic resonator as shown in Figure 1-3( external clock signal as shown in Figure 1-3(b) The frequency the oscillator or external clock source is divided by two to OSC produce the internal operating frequency, f 3MHZ, then the external oscillator frequency will be 6MHz. For LS USB 1.5MHz frequency clock can be derived from a divided by 4 circuit ...
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... In Bootloader mode, this pin (VPP) is used to supply the required programming voltage to the EPROM array. 1-6 For More Information On This Product, August 28, 1998 , when the power is removed for "wired-OR" operation, if desired. The IRQ pin contains NOTE GENERAL DESCRIPTION Go to: www.freescale.com . The RESET pin DD MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 1.4.5 PA0-PA7 These eight I/O lines comprise PortA. PA0 to PA7 are push-pull pins with pulldown devices. PA4 to PA7 are also capable of sinking 8 mA. The state of any pin is software programmable and all Port A lines are configured as inputs during power-on or reset. The lower four I/O pins (PA0 thru PA3) can be connected via an internal OR gate to the IRQ interrupt function enabled by a mask option ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1-8 For More Information On This Product, August 28, 1998 GENERAL DESCRIPTION Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 2.1 MEMORY MAP The MC68HC705JB2 has an 8-Kbyte memory map consisting of user EPROM, RAM, burn-in ROM, and input/output (I/O), as shown in Figure 2-1. $0000 0000 I/O 64 Bytes $003F 0063 0064 $0040 unimplemented 64 Bytes 0127 $007F 0128 $0080 User RAM 128 Bytes $00C0 Stack 0255 ...
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... USB Control2 Register $0037 $0038 USB Address Register USB Interrupt0 Register $0039 USB Interrupt1 Register $003A USB Control0 Register $003B USB Control1 Register $003C USB Status Register $003D $003E $003F Reserved Mask Option Register $01FF Figure 2-2. I/O Registers MEMORY Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 2.3 RAM The user RAM consists of 128 bytes (including the stack) located from $0080 to $00FF. The stack begins at address $00FF and proceeds down to $00C0. Using the stack area for data storage or temporary work locations requires care to pre- vent it from being overwritten due to stacking from an interrupt or subroutine call. ...
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... TOF RTIF TOFE RTIE TMR7 TMR6 TMR5 TMR4 IRQE MEMORY Go to: www.freescale.com BIT 3 BIT 2 BIT 1 BIT 0 PA3 PA2 PA1 PA0 PB2 PB1 PB0 DDRB2 DDRB1 DDRB0 0 0 RT1 RT0 TOFR RTIFR TMR3 TMR2 TMR1 TMR0 IRQF IRQR MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. ADDR REGISTER R/W R PORT A PULLDOWN/UP $0010 (PDURA PORT B PULLDOWN/UP $0011 (PDURB) W TIMER CONTROL R $0012 (TCR) W TIMER STATUS R $0013 (TSR) W INPUT CAPTURE HIGH R $0014 (ICH INPUT CAPTURE LOW $0015 (ICL OUTPUT COMPARE HIGH $0016 (OCH OUTPUT COMPARE LOW ...
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... IRQTRIG PULLREN PAINTEN OSCDLY MEMORY Go to: www.freescale.com BIT 3 BIT 2 BIT 1 BIT 0 STALL2 STALL1 ENABLE2 ENABLE1 0 0 TXD0FR RXD0FR 0 0 TXD1IE EOPIE TXD1FR EOPFR TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0 MORON ELAT PGM BIT 3 BIT 2 BIT 1 BIT 0 LVREN MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT The MC68HC705JB2 has a 8Kbyte memory map. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap-around to $00FF. All other instructions and registers behave as described in this chapter. ...
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... If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack and an interrupt uses five locations. 3-2 For More Information On This Product, August 28, 1998 CENTRAL PROCESSING UNIT Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 3.5 PROGRAM COUNTER (PC) The program counter shown in Figure 3 16-bit register. In MCU devices with memory space less than 64 Kbytes the unimplemented upper address lines are ignored. The program counter contains the address of the next instruction or operand to be fetched. Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched ...
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... The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction. 3-4 For More Information On This Product, August 28, 1998 CENTRAL PROCESSING UNIT Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. The MCU can be interrupted in six different ways: • Non-maskable Software Interrupt Instruction (SWI) • External Interrupt (IRQ) • Optional External Interrupt via IRQ on PA0-PA3 (mask option) • USB Interrupt • Timer1 Interrupt (16-bit Timer) • Multi-Function Timer Interrupt 4 ...
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... I Bit RTIE Bit Reserved Reserved INTERRUPTS Go to: www.freescale.com Priority Vector (1 = Highest) Address 1 $1FFE–$1FFF Same Priority $1FFC–$1FFD As Instruction 2 $1FFA–$1FFB 3 $1FF8–$1FF9 4 $1FF6–$1FF7 5 $1FF4–$1FF5 $1FF2–$1FF3 $1FF0–$1FF1 MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. FROM RESET YES I BIT SET? NO EXTERNAL INTERRUPT? NO USB INTERRUPT? NO TIMER1 INTERRUPT? NO MFT INTERRUPT? NO FETCH NEXT INSTRUCTION. SWI INSTRUCTION? NO RTI INSTRUCTION? NO Figure 4-1. Interrupt Processing Flowchart REV 1.1 For More Information On This Product, August 28, 1998 GENERAL RELEASE SPECIFICATION YES CLEAR IRQ LATCH. ...
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... Port A External Interrupt (Mask Option) IRQ VECTOR FETCH Figure 4-2. External Interrupt (IRQ) Logic 4-4 For More Information On This Product, August 28, 1998 V DD IRQ LATCH R RST IRQ STATUS/CONTROL REGISTER INTERNAL DATA BUS INTERRUPTS Go to: www.freescale.com TO BIH & BIL INSTRUCTION PROCESSING EXTERNAL INTERRUPT REQUEST MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. The IRQ pin is one source of an IRQ interrupt and a mask option can also enable the four lower Port A pins (PA0 thru PA3) to act as other IRQ interrupt sources. Refer to Figure 4-2 for the following descriptions. IRQ interrupt source comes from IRQ latch. The IRQ latch will be set on the falling edge of the IRQ pin or on any rising edge of PA0-3 pins if PA0-3 interrupts have been enabled. If " ...
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... OR’ed with the input present on the IRQ pin. All PA0 thru PA3 pins must be selected as a group as an additional IRQ interrupt. All the PA0-3 interrupt sources are also controlled by the IRQE enable bit. 4-6 For More Information On This Product, August 28, 1998 INTERRUPTS Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and not to the output of the logic OR function with the PA0 thru PA3 pins. The state of the individual Port A pins can be checked by reading the appropriate Port A pins as inputs. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 4-8 For More Information On This Product, August 28, 1998 INTERRUPTS Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. The MCU can be reset in five ways: • active low input to the RESET pin, • by initial power-on reset, • USB reset, • illegal address access, and • low voltage reset function. The RESET pin is an I/O pin as shown in Figure 5-1. The internal steering diode for discharge and pull-up device are not shown here ...
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... USB Reset The USB reset is generated by a detection on the USB bus reset signal. For MC68HC705JB2, seeing a single-end zero on its upstream port for bit times will set RSTF bit in UIR0 register. The detections will also generate the RST signal to reset the CPU and other peripherals in the MCU. ...
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... Freescale Semiconductor, Inc. 5.2.3 Illegal Address Reset (ILADR) The internal ILADR reset is generated when an instruction opcode fetch occurs from an address which is not implemented in the RAM ($0080 - $00FF) nor ROM ($1600-$1FFF). The ILADR will generate the RST signal which will reset the CPU and other peripherals ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 5-4 For More Information On This Product, August 28, 1998 RESETS Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. The MC68HC705JB2 has two low-power operating modes: STOP mode and WAIT mode. The STOP and WAIT instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the oscillator. The flow of the STOP, and WAIT modes are shown in Figure 6-1. ...
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... INTERNAL TIMER CLOCK ACTIVE STOP INTERNAL PROCESSOR CLOCK, YES OR LOW POWER MODES Go to: www.freescale.com WAIT CLEAR I-BIT IN CCR, SET IRQE IN ICSR YES EXTERNAL RESET? NO IRQ YES EXTERNAL INTERRUPT? NO USB YES RESET OR INTERRUPT? NO TIMER1 YES INTERNAL INTERRUPT? NO MFT YES INTERNAL INTERRUPT? NO MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 6.3 DATA-RETENTION MODE The contents of RAM and CPU registers are retained at supply voltages as low as 2.0Vdc. This is called the data-retention mode where the data is held, but the device is not guaranteed to operate. The RESET pin must be held low during data-retention mode. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 6-4 For More Information On This Product, August 28, 1998 LOW POWER MODES Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. In the Normal Operating Mode, there are 11 bidirectional I/O lines arranged as one 8-bit I/O port (Port A), and one 3-bit I/O port (Port B). Each port line can be programed as either input or output, under software control, by the data direction registers (DDR’s). Also, if enabled by a mask option, all Port A and Port B I/O pins may have individual software programmable pulldown or pullup devices. PA4 to PA7 and PB1 & ...
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... DDRA. The DDRA can be accessed at address $0004. The DDRA is cleared by reset. 7-2 For More Information On This Product, August 28, 1998 Data Pulldown Mask Option (Software Pulldown Inhibit) INPUT/OUTPUT PORTS Go to: www.freescale.com Output I/O Pin 8 mA Sink Capability (Bits 4-7 Only) 100 A Pulldown PA0-PA3 only: to IRQ interrupt system MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 7.1.3 Port A Pulldown Register All Port A I/O pins may have software programmable pulldown devices enabled by a mask option. If the pulldown/up mask option is selected, the pulldown is activated whenever the corresponding bit in the PDURA is clear. If the corresponding bit in the PDURA bit is set or the mask option for pulldown is not chosen, the pulldown will be disabled ...
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... The Port B data register is unaffected by reset. 7-4 For More Information On This Product, August 28, 1998 0.5V max. These two pins may be connected OL Register Bit Data Register Bit Register Bit Mask Option INPUT/OUTPUT PORTS Go to: www.freescale.com VDD 100K Pullup Output I/O Pin 100 A Pulldown MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 7.2.2 Port B Data Direction Register Port B I/O pins may be programmed as an input by clearing the corresponding bit in the DDRB, or programmed as an output by setting the corresponding bit in the DDRB. The DDRB can be accessed at address $0005. Unused bits will always read as logic zeros, and any write to these bits will be ignored. The DDRB is cleared by reset. If confi ...
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... If the corresponding bit in the pulldown/up register is clear (and the pulldown/up mask option is chosen) the input pin will also have an activated pulldown/up device. Since the pulldown/up register bits are write-only, bit manipulation should not be used on these register bits. 7-6 For More Information On This Product, August 28, 1998 INPUT/OUTPUT PORTS Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 7.3.4 I/O Pin Transitions A "glitch" can be generated on an I/O pin when changing it from an input to an output unless the data register is first preconditioned to the desired state before changing the corresponding DDR bit from a zero to a one. If pulldowns are enabled by mask option, a floating input can be avoided by clearing the pulldown/pullup register bit before changing the corresponding DDR from a one to a zero ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7-8 For More Information On This Product, August 28, 1998 INPUT/OUTPUT PORTS Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. MULTI-FUNCTION TIMER The MC68HC705JB2 core timer is a multi-function ripple counter. The features include Timer Over Flow (TOF) and Power-On Reset (POR Timer Counter Register ($09 RTI Select Circuit Overflow Detect Circuit Timer Control & Status Register ($08) ...
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... Two additional stages produce the POR function op /16384) driving the Real Time Interrupt circuit. op BIT 5 BIT 4 BIT 3 TMR5 TMR4 TMR3 MULTI-FUNCTION TIMER Go to: www.freescale.com 14 /2 (or f /16384 BIT 2 BIT 1 BIT 0 TMR2 TMR1 TMR0 MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 8.1.2 Timer Control/Status Register (TCSR) $08 The TCSR contains the timer interrupt flag bits, the timer interrupt enable bits, and the real time interrupt rate select bits. Bit 2 and bit 3 are write-only bits which will read as logical zeros. Figure 8-3 shows the value of each bit in the TCSR following reset ...
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... RESET, the internal oscillator will resume, followed by a 128 or 4064 internal processor oscillator stabilization delay. 8-4 For More Information On This Product, August 28, 1998 Bus Frequency =3.0 MHz BUS OP Divide Ratio RTI Rate 14 2 5.46ms 15 2 10.92ms 16 2 21.85ms 17 2 43.69ms MULTI-FUNCTION TIMER Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. PROGRAMMABLE TIMER This 16-bit Programmable Timer (Timer1) has an Input Capture function and an Output Compare function. Figure 9-1 shows a block diagram of the 16-bit programmable timer. EDGE SELECT TCAP & DETECT LOGIC RESET TIMER CONTROL REGISTER $0012 INTERNAL DATA BUS Figure 9-1. Programmable Timer Block Diagram REV 1 ...
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... Figure 9-2. Programmable Timer Counter Block Diagram 9-2 For More Information On This Product, August 28, 1998 LATCH TMRL ($0019) TMRH ($0018) TMR LSB 16-BIT COUNTER OVERFLOW (TOF) TIMER STATUS REG. PROGRAMMABLE TIMER Go to: www.freescale.com READ TMRL INTERNAL 4 CLOCK (f 2) OSC TIMER INTERRUPT REQUEST $0013 INTERNAL DATA BUS MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC. BIT 7 BIT 6 ...
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... COUNTER BIT 5 BIT 4 BIT 3 ACRH5 ACRH4 ACRH3 ACRL5 ACRL4 ACRL3 PROGRAMMABLE TIMER Go to: www.freescale.com INTERNAL DATA BUS READ ACRL INTERNAL 4 CLOCK (f 2) OSC BIT 2 BIT 1 BIT 0 ACRH2 ACRH1 ACRH0 ACRL2 ACRL1 ACRL0 MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. To prevent interrupts from occurring between readings of the ACRH and ACRL, set the I bit in the condition code register (CCR) before reading ACRH and clear the I bit after reading ACRL. 9.3 INPUT CAPTURE REGISTERS The input capture function is a technique whereby an external signal (connected to PB0/TCAP pin) is used to trigger the 16-bit timer counter ...
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... OCIE=1. 9-6 For More Information On This Product, August 28, 1998 BIT 5 BIT 4 BIT 3 ICRH5 ICRH4 ICRH3 ICRL5 ICRL4 ICRL3 NOTE PROGRAMMABLE TIMER Go to: www.freescale.com BIT 2 BIT 1 BIT 0 ICRH2 ICRH1 ICRH0 ICRL2 ICRL1 ICRL0 MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. Software can use the output compare register to measure time periods, to generate timing delays generate a pulse of specific duration or a pulse train of specific frequency and duty cycle. Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written. Reading or writing to the OCRL after reading the TSR will clear the output compare fl ...
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... August 28, 1998 DISABLE INTERRUPTS ..... ..... OCRH INHIBIT OUTPUT COMPARE TSR ARM OCF FLAG FOR CLEARING OCRL READY FOR NEXT COMPARE, OCF CLEARED ..... ..... ENABLE INTERRUPTS BIT 5 BIT 4 BIT TOIE PROGRAMMABLE TIMER Go to: www.freescale.com BIT 2 BIT 1 BIT IEDG 0 Unaffected 0 MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. OCIE - OUTPUT COMPARE INTERRUPT ENABLE This read/write bit enables interrupts caused by a successful compare between the timer counter and the output compare registers. Reset clears the OCIE bit Output compare interrupts enabled Output compare interrupts disabled. TOIE - TIMER OVERFLOW INTERRUPT ENABLE This read/write bit enables interrupts caused by a timer overfl ...
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... If the STOP mode is exited by an external reset, no input capture flag or data will be present even if a valid input capture edge was detected during the STOP mode. 9-10 For More Information On This Product, August 28, 1998 PROGRAMMABLE TIMER Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. UNIVERSAL SERIAL BUS MODULE This USB Module is designed for USB application in LS products. With minimized software effort, it can fully comply with USB LS device specification. See USB specification version 1.0 for the detail description of USB. 10.1 FEATURES • Integrated 3.3 Volt Regulator with 3.3V Output Pin • ...
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... OVERVIEW This section provides an overview of the Universal Serial Bus (USB) module in the MC68HC705JB2. This USB module is designed to serve as a low-speed (LS) USB device per the Universal Serial Bus Specification Rev 1.0. Three types of USB data transfers are supported: control, interrupt, and bulk (transmit only). ...
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... IN DATA0/1 Figure 10-2. Supported Transaction Types per Endpoint Each USB transaction is comprised of a series of packets. The MC68HC705JB2 USB module supports the packet types shown in Figure 10-3. Token packets are generated by the USB host and decoded by the USB device. Data and Handshake packets are both decoded and generated by the USB device depending on the type of transaction ...
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... UNIVERSAL SERIAL BUS MODULE 10-4 For More Information On This Product, August 28, 1998 SYNC PID PID ADDR SYNC PID PID SYNC PID PID EOP SYNC PATTERN Figure 10-4. Sync Pattern Go to: www.freescale.com ENDP CRC5 EOP DATA CRC5 EOP bytes PID0 PID1 MC68HC705JB2 REV 1.1 ...
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... Address Field (ADDR) The Address field is a seven bit number that is used to select a particular USB device. This field is compared to the lower seven bits of the UADDR register to determine if a given transaction is targeting the MC68HC705JB2 USB device. UNIVERSAL SERIAL BUS MODULE REV 1.1 For More Information On This Product, ...
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... GENERAL RELEASE SPECIFICATION 10.2.1.4 Endpoint Field (ENDP) The Endpoint field is a four bit number that is used to select a particular endpoint within a USB device. For the MC68HC705JB2, this will be a binary number between zero and two inclusive. Any other value will cause the transaction to be ignored. ...
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... Freescale Semiconductor, Inc. Update every bit time Reset to ones at SOP Input / Output Data Stream next bit Output TRANSMIT Data Stream CRC16 Transmitted MSB first after final data byte. Figure 10-7. CRC Block Diagram for Data Packets 10.2.1.6 End Of Packet (EOP) The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The single-ended 0 state is indicated by both D+ and D- being below 0 ...
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... Low speed device, an SE0 condition between 4 and 8 low speed bit times represents a valid USB reset. A USB sourced reset will hold the MC68HC705JB2 in reset for the duration of the reset on the USB bus. The RSTF bit in the USB interrupt register 0 (UIR0) will be set after the internal reset is removed (See Section 10.5.2 for more detail). ...
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... STOP mode once the USB module has been placed in the suspend state. 10.2.4 Resume After Suspend The MC68HC705JB2 can be activated from the suspend state by normal bus activity, a USB reset signal forced resume driven from the MC68HC705JB2. 10.2.4.1 Host Initiated Resume The host signals resume by initiating resume signalling (“ ...
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... Low Speed Device Externally, low speed devices are configured by the position of a pull-up resistor on the USB D- pin of the MC68HC705JB2. Low speed devices are terminated as shown in Figure 10-10 with the pull-up on the D- line. 68HC705JB2 Figure 10-10. External Low Speed Device Confi ...
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... Freescale Semiconductor, Inc. 10.3 CLOCK REQUIREMENTS The low speed data rate is nominally 1.5 Mbs. The OSCXCLK signal driven by the oscillator circuits is the clock source for the USB module and requires that a 6 MHz oscillator circuit be connected to the OSC1 and OSC2 pins. The permitted frequency tolerance for low speed functions is approximately 1 ...
Page 80
... UNIVERSAL SERIAL BUS MODULE 10-12 For More Information On This Product, August 28, 1998 load to 3.6 V and in its high state is above the V load to ground. The output swings between the differential SIGNAL PINS PASS OUTPUT SPEC LEVELS WITH MINIMAL REFLECTIONS AND RINGING Go to: www.freescale.com OH MC68HC705JB2 REV 1.1 ...
Page 81
... Freescale Semiconductor, Inc. 10.4.3 Receiver Characteristics USB data transmission is done with differential signals. A differential input receiver is used to accept the USB data signal. A differential 1 on the bus is represented by D+ being at least 200 mV more positive than D- as seen at the receiver, and a differential 0 is represented by D- being at least 200 mV more positive than D+ as seen at the receiver ...
Page 82
... TRANSITIONS PAIRED TRANSITIONS Figure 10-14. Data Jitter 25 ns and within 10 ns for any set of paired ) and 300 ns (maximum) into a L RISE TIME 90% 90% 10 LOW SPEED: 75ns 50pF, 300ns to: www.freescale.com PERIOD is PERIOD FALL TIME 10 350pF L MC68HC705JB2 REV 1.1 ...
Page 83
... Freescale Semiconductor, Inc. 10.4.4 USB Control Logic The USB control logic manages data movement between the CPU and the transceiver. The control logic handles both transmit and receive operations on the USB. It contains the logic used to manipulate the transceiver and the endpoint registers. The logic contains byte count buffers for transmit operations that load the active transmit endpoints byte count and use this to determine the number of bytes to transfer ...
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... FETCH THE DATA BIT IS DATA YES NO BIT = 0? NO DATA TRANSITION TRANSITION DATA IS PACKAGE NO YES TRANSFER DONE? SYNC PATTERN PACKET DATA PACKET DATA SYNC PATTERN SIX ONES PACKET DATA SYNC PATTERN Figure 10-18. Bit Stuffing Go to: www.freescale.com STUFFED BIT MC68HC705JB2 REV 1.1 ...
Page 85
... Freescale Semiconductor, Inc. NO PACKET TRANSMISSION Figure 10-19. Flow Diagram for Bit Stuffing UNIVERSAL SERIAL BUS MODULE REV 1.1 For More Information On This Product, August 28, 1998 GENERAL RELEASE SPECIFICATION POWER UP IDLE BEGIN PACKET TRANSMISSION RESET BIT COUNTER TO 0 GET NEXT BIT = BIT VALUE? ...
Page 86
... UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 = Unimplemented Go to: www.freescale.com 2 1 Bit 0 Addr STALL1 $0037 UADD2 UADD1 UADD0 $0038 0 0 RXD0IE $0039 TXD0FR RXD0FR 0 0 EOPIE $003A TXD1FR EOPFR RPSIZ2 RPSIZ1 RPSIZ0 $003D $0020 $0027 $0028 $002F MC68HC705JB2 REV 1.1 ...
Page 87
... Freescale Semiconductor, Inc. 10.5.1 USB Address Register (UADDR) Bit 7 UADDR R USBEN UADD6 $0038 W reset 0 Figure 10-20. USB Address Register (UADDR) USBEN — USB Module Enable This read/write bit enables and disables the USB module and the USB pins. When USBEN is clear, the USB module will not respond to any tokens. Reset clears this bit ...
Page 88
... EOPF $003A W reset 0 = Unimplemented Figure 10-22. USB Interrupt Register 1(UIR1) UNIVERSAL SERIAL BUS MODULE 10-20 For More Information On This Product, August 28, 1998 Bit 6 Bit 5 Bit 4 Bit 3 RESUMF 0 TXD1IE RESUMFR to: www.freescale.com Bit 2 Bit 1 Bit EOPIE TXD1FR EOPFR MC68HC705JB2 REV 1.1 ...
Page 89
... Freescale Semiconductor, Inc. TXD1F — Endpoint 1/Endpoint 2 Data Transmit Flag This read only bit is shared by Endpoint 1 and Endpoint set after the data stored in the shared Endpoint 1/Endpoint 2 transmit buffer has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this fl ...
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... Data is ready to be received Not ready for data. Respond with NAK. UNIVERSAL SERIAL BUS MODULE 10-22 For More Information On This Product, August 28, 1998 Bit 6 Bit 5 Bit 4 Bit 3 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 to: www.freescale.com Bit 2 Bit 1 Bit MC68HC705JB2 REV 1.1 ...
Page 91
... Freescale Semiconductor, Inc. TP0SIZ3-TP0SIZ0 — Endpoint 0 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for Endpoint 0. These bits are cleared by reset. 10.5.5 USB Control Register 1 (UCR1) Bit 7 UCR1 R T1SEQ ENDADD $003C W reset 0 Figure 10-24 ...
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... IN or OUT token by the USB Host Controller. Reset clears this bit Send STALL handshake Default UNIVERSAL SERIAL BUS MODULE 10-24 For More Information On This Product, August 28, 1998 Bit 6 Bit 5 Bit 4 Bit 3 0 TX1ST 0 ENABLE2 ENABLE1 - to: www.freescale.com Bit 2 Bit 1 Bit 0 STALL2 STALL1 MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. STALL1 — Endpoint 1 Force Stall Bit This read/write bit causes Endpoint 1 to return a STALL handshake when polled by either OUT token by the USB Host Controller. Reset clears this bit Send STALL handshake 0 = Default 10.5.7 USB Status Register (USR) Bit 7 ...
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... Endpoints 1 and 2 and depend on proper configuration of the ENDADD bit. UNIVERSAL SERIAL BUS MODULE 10-26 For More Information On This Product, August 28, 1998 Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit to: www.freescale.com Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit MC68HC705JB2 REV 1.1 ...
Page 95
... Freescale Semiconductor, Inc. 10.6 USB INTERRUPTS The USB module is capable of generating interrupts and causing the CPU to execute the USB interrupt service routine. There are three types of USB interrupts: • End of Transaction interrupts signify a completed transaction (receive or transmit) • Resume interrupts signify that the USB bus is reactivated after having been suspended • ...
Page 96
... UIR1 register. There is no interrupt enable bit for this interrupt source and an interrupt will be executed if the I bit in the CCR is cleared. A resume interrupt can only occur while the MC68HC705JB2 is in the suspend mode. 10.6.3 End of Packet Interrupt The USB module can generate a USB interrupt upon detection of an end of packet signal (a single ended 0) for low speed devices ...
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... Freescale Semiconductor, Inc. Valid OUT token received for Endpoint 0 Y Valid DATA token received for Endpoint 0? Y Endpoint 0 Receive Enabled? (USBEN = 1) Y Endpoint 0 Receive Not Stalled? (STALL0 = 0) Y Endpoint 0 Receive Ready to Receive? (RX0E = 1) && (RXD0F = 0) Y Accept Data Set/clear RSEQ bit ...
Page 98
... Figure 10-30. SETUP Token Data Flow for Receive Endpoint 0 UNIVERSAL SERIAL BUS MODULE 10-30 For More Information On This Product, August 28, 1998 N No Response from USB function N No Response from USB function N Clear STALL0 bit Ignore transaction N No response from USB function N Go to: www.freescale.com No Interrupt MC68HC705JB2 REV 1.1 ...
Page 99
... Freescale Semiconductor, Inc. Valid IN token received for Endpoint 0 Y Transmit Endpoint Enabled? (USBEN = 1) Y Transmit Endpoint not Stalled by firmware? (STALL0 = 0) Y Transmit Endpoint ready to Transfer? (TX0E = 1) && (TXD0F = 0) Y Send DATA Data PID set by T0SEQ ACK received and no Time-out condition occur? ...
Page 100
... UNIVERSAL SERIAL BUS MODULE 10-32 For More Information On This Product, August 28, 1998 N No Response from USB function Response from USB function Note: ENDP1 is Endpoint 1 directed traffic ENDP2 is Endpoint 2 directed traffic Go to: www.freescale.com Send STALL Handshake Send NAK Handshake No Interrupt MC68HC705JB2 REV 1.1 ...
Page 101
... Freescale Semiconductor, Inc. This section describes erasable programmable read-only memory (EPROM) programming. 11.1 EPROM The on-chip user EPROM consists of 2048 bytes of EPROM from $1600 to $1DFF and 16 bytes of user vectors from $1FF0 to $1FFF. The bootloader ROM and vectors are located from $1E00 to $1FEF. ...
Page 102
... Clear the ELAT bit The last two steps must be performed with separate CPU writes. 11-2 For More Information On This Product, August 28, 1998 bit-5 bit4 bit-3 RESERVED PGMR EPROM Go to: www.freescale.com bit-2 bit1 bit-0 ELAT PGM MORON pin MC68HC705JB2 REV 1.1 ...
Page 103
... Freescale Semiconductor, Inc important to remember that an external programming voltage must be applied to the V equal to V during normal operations. DD Figure 11-1 shows the flow required to successfully program the EPROM. Figure 11-1. EPROM Programming Sequence REV 1.1 For More Information On This Product, August 28, 1998 GENERAL RELEASE SPECIFICATION ...
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... LVREN – LVR Option 1 = Enabled 0 = Disabled 11-4 For More Information On This Product, August 28, 1998 bit-5 bit4 bit-3 IRQTRIG PULLREN Unaffected EPROM Go to: www.freescale.com bit-2 bit1 bit-0 PAINTEN OSCDLY LVREN MC68HC705JB2 REV 1.1 ...
Page 105
... Freescale Semiconductor, Inc. This section describes the addressing modes and instruction types. 12.1 ADDRESSING MODES The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are the following: • ...
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... The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 12-2 For More Information On This Product, August 28, 1998 INSTRUCTION SET Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 12.1.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The fi ...
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... Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator 12-4 For More Information On This Product, August 28, 1998 Instruction INSTRUCTION SET Go to: www.freescale.com Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 12.1.11 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. The test for negative or zero instruction (TST exception to the read-modify-write sequence because it does not write a replacement value. Table 12-2 lists the read-modify-write instructions ...
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... Unconditional Jump Jump to Subroutine 12-6 For More Information On This Product, August 28, 1998 Instruction Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR INSTRUCTION SET Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 12.1.13 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the fi ...
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... INH 47 3 INH 57 3 IX1 REL DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 REL REL MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Continued) Source Operation Form Branch if Half-Carry BHCC rel Bit Clear Branch if Half-Carry BHCS rel Bit Set BHI rel Branch if Higher Branch if Higher or BHS rel Same Branch if IRQ Pin BIH rel High Branch if IRQ Pin ...
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... DIR EXT IX2 IX1 DIR INH 4A 3 — INH 5A 3 IX1 IMM DIR EXT — IX2 IX1 MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Continued) Source Operation Form INC opr INCA INCX Increment Byte INC opr ,X INC ,X JMP opr JMP opr JMP opr ,X Unconditional Jump JMP opr ,X JMP ,X JSR opr JSR opr JSR opr ,X Jump to Subroutine JSR opr ,X ...
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... IX2 IX1 INH 99 2 INH 9B 2 DIR EXT — IX2 IX1 INH 8E 2 DIR EXT — IX2 IX1 MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Continued) Source Operation Form SUB # opr SUB opr Subtract Memory SUB opr Byte from SUB opr ,X Accumulator SUB opr ,X SUB ,X SWI Software Interrupt Transfer TAX Accumulator to Index Register TST opr TSTA Test Memory Byte ...
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... Freescale Semiconductor, Inc. 1.1 REV MC68HC705JB2 For More Information On This Product, SET INSTRUCTION Go to: www.freescale.com 12-14 MOTOROLA ...
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... Freescale Semiconductor, Inc. ELECTRICAL SPECIFICATIONS 13.1 MAXIMUM RATINGS Table 13-1. Maximum Ratings (Voltages referenced Rating Supply Voltage Input Voltage EPROM Programming Voltage Current Drain Per Pin Excluding PB1, PB2, V Operating Temperature Range (Standard) (Extended) Storage Temperature Range This device contains circuitry to protect the inputs against damage due to high static voltages or electric fi ...
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... Go to: www.freescale.com Typ Max Unit — 0.1 V — — — — V — 0.4 V — 0.4 — 0.5 — — 0 4.0 2 8.8 mA 2.0 1.0 mA 200 250 A 300 400 A — 100 200 A — — — 2.0 3.0 M 100 200 K 3.3 3.6 V 3.5 3.7 V MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. NOTES: 1. All values shown reflect average measurements. 2. Typical values at midpoint of voltage range only. 3. Wait I : Only timer system (MFT) active Run (Operating Wait I : Measured using external square wave clock source to OSC1 ( rail loads, less than 50pF on all outputs ...
Page 122
... Note 7 and TEOPT 1.25 Figure 12-3 Note 7 and TDEOP –40 Figure 12-3 Note 7 and T 330 EOPR1 Figure 12-3 T 675 EOPR2 ELECTRICAL SPECIFICATIONS Go to: www.freescale.com Typ Max Unit ns 300 ns ns 300 ns 120 % 2.0 V 1.500 1.5225 Mbs 666.0 656 1.50 s 100 MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. 13.6 CONTROL TIMING (V = 4.2V to 5.5V Vdc Characteristic Frequency of Operation Crystal Oscillator Option External Clock Source Internal Operating Frequency Crystal Oscillator (f 2) OSC External Clock (f 2) OSC Cycle Time (1 RESET Pulse Width Low IRQ Interrupt Pulse Width Low (Edge-Triggered) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13-6 For More Information On This Product, August 28, 1998 ELECTRICAL SPECIFICATIONS Go to: www.freescale.com MC68HC705JB2 REV 1.1 ...
Page 125
... Freescale Semiconductor, Inc. MECHANICAL SPECIFICATIONS This section provides the mechanical dimensions for the two available packages for MC68HC705JB2: the 20-Pin PDIP and 20-Pin SOIC. 14.1 20-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) –A– –T– SEATING PLANE ...
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... TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 MC68HC705JB2 REV 1.1 ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...