mc68307ad Freescale Semiconductor, Inc, mc68307ad Datasheet

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mc68307ad

Manufacturer Part Number
mc68307ad
Description
Integrated Multiple-bus Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
SEMICONDUCTOR
TECHNICAL INFORMATION
MOTOROLA
Technical Summary
Integrated Multiple-Bus Processor
The MC68307 is an integrated processor combining a static 68EC000 processor with multiple interchip bus
interfaces. The MC68307 is designed to provide optimal integration and performance for applications such as
digital cordless telephones, portable measuring equipment, and point-of-sale terminals. By providing 3.3 V,
static operation in a small package, the MC68307 delivers cost-effective performance to handheld, battery-
powered applications.
The MC68307 (shown in Figure 1) contains a static EC000 core processor, multiple bus interfaces, a serial
channel, two timers, and common system glue logic. The multiple bus interfaces include: dynamic 68000 bus,
8051 bus, and Motorola bus (M-bus) or I
out of static random access memory (SRAM) while still providing a low-cost interface to an 8-bit read-only
memory (ROM). The 8051 bus interfaces gluelessly to 8051-type devices and allows the reuse of application-
specific integrated circuits (ASICs) designed for this industry standard bus. The M-bus is an industry standard
2-wire interface which provides efficient communications with peripherals such as EEPROM, analog/digital (A/
D) converters, and liquid crystal display (LCD) drivers. Thus, the MC68307 interfaces gluelessly to boot ROM,
SRAM, 8051 devices, M-bus devices, and memory-mapped peripherals. The MC68307 also incorporates a
slave mode which allows the EC000 core to be turned off, providing a 3.3-V static, low-power multi-function
peripheral for higher performance M68000 family processors.
MOTOROLA, 1993
1.
I
2
C bus is a proprietary Philips interface bus.
SYSTEM INTEGRATION MODULE
PROCESSOR CONTROL, CLOCK
(Parts Not Suitable for New Designs)
CHIP SELECT AND DTACK
SYSTEM PROTECTION
8051 BUS INTERFACE
PARALLEL I/O PORTS
AND LOW POWER
Thi d
BUS INTERFACE
8/16-BIT M68000
CONTROLLER
INTERRUPT
JTAG PORT
(SIM07)
Figure 1. MC68307 Block Diagram
2
C bus
t
1
. The dynamically sized 68000 bus allows 16-bit performance
t d ith F
MODULE
M-BUS
STATIC EC000 CORE PROCESSOR
DYNAMIC BUS SIZING EXTENSION
68000 INTERNAL BUS
M k 4 0 2
SERIAL I/O
UART
MC68307V
MODULE
TIMER
DUAL
MC68307
Order this document by
MC68307/D

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mc68307ad Summary of contents

Page 1

MOTOROLA (Parts Not Suitable for New Designs) SEMICONDUCTOR TECHNICAL INFORMATION Technical Summary Integrated Multiple-Bus Processor The MC68307 is an integrated processor combining a static 68EC000 processor with multiple interchip bus interfaces. The MC68307 is designed to provide optimal integration and ...

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The main features of the MC68307 include: • Static EC000 Core Processor—Identical to MC68EC000 Microprocessor — Full compatibility with MC68000 and MC68EC000 — 24-bit address bus, for 16-Mbyte off-chip address space — 16-bit on-chip data bus for MC68000 bus operations ...

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The MC68307 is one of a series of components in Motorola's M68300 family. Other members of the family include the MC68302, MC68306, MC68330, MC68331, MC68332, MC68F333, MC68334, MC68340, MC68341, MC68349, and MC68360. ORGANIZATION The M68300 family of integrated processors and ...

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To improve total system throughput and reduce part count, board size and cost of system implementation, the MC68307 integrates a powerful processor, intelligent peripheral modules, and typical system interface logic. These functions include the SIM07, timers, UART, M-bus interface, and ...

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Figure 3. Supervisor Programming Model Supplement TRACE MODE SUPERVISOR STATE INTERRUPT MASK EXTEND NEGATIVE CONDITION CODES OVERFLOW MOTOROLA Figure 2. User Programming Model SYSTEM BYTE 15 13 ...

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Data Types and Addressing Modes Five basic data types are supported: 1.) Bits 2.) Binary coded decimal (BCD) digits (4 bits) 3.) Bytes (8 bits) 4.) Words (16 bits) 5.) Long words (32 bits) In addition, operations on other data ...

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Register direct addressing Absolute data addressing Program counter relative addressing Register indirect addressing register Immediate data addressing Implied addressing Legend Data Register An = Address Register Xn = Address or Data Register Used as Index Register SR = ...

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Mnemonic ABCD Add decimal with extend ADD Add ADDA Add address ADDQ Add quick ADDI Add immediate ADDX Add with extend AND Logical AND ANDI AND immediate ANDI to CCR AND immediate to condition codes ANDI to SR AND immediate ...

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SYSTEM INTEGRATION MODULE The MC68307 system integration module (SIM07) consists of several functions that control the system start-up, initialization, configuration, and the external bus with a minimum of external devices. The SIM07 features include: • System configuration • Oscillator & ...

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External Bus Interface The external bus interface handles the transfer of information between the internal EC000 core and the memory, peripherals, or other processing elements in the external address space. It consists of a 68000 bus interface and an 8051-compatible ...

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Low-Power Stop Logic Various options for power-saving are available: turning off unused peripherals, reducing processor clock speed, disabling the processor altogether or a combination of these. A wake-up from power-down can be achieved by causing an interrupt at the interrupt ...

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MBASE+$040 MBASE+$042 MBASE+$044 MBASE+$046 MBASE+$048 MBASE+$04A MBASE+$04C MBASE+$04E Table 5. SIM07 External Bus Interface Registers Address FC MBASE+$011 S/U MBASE+$013 S/U MBASE+$015 S/U MBASE+$016 S/U MBASE+$018 S/U MBASE+$01A S/U Table 6. SIM07 Interrupt Controller Registers Address FC MBASE+$020 S/U MBASE+$022 ...

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DUAL TIMER MODULE The MC68307 includes two independent, identical, general-purpose timers. Each general-purpose timer block contains a free-running 16-bit timer which can be used in various modes, to capture the timer value with an external event, to trigger an external ...

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M-BUS INTERFACE MODULE The M-bus is a two-wire, bidirectional serial bus which provides a simple and efficient means of data exchange between devices fully compatible with the I at 16.67-MHz system clock speed. The maximum communication length and ...

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UART MODULE The UART module in the MC68307 is based on the MC68681 DUART, which is part of the M68000 family of peripherals which directly interfaces to the MC68000 processor via an asynchronous bus structure. The UART module consists of ...

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UART Programming Model The programming model for the UART module is listed in Table 10. The FC (function code) column indicates whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user space ...

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EXTERNAL SIGNAL DESCRIPTIONS Figure 5 shows the MC68307 input and output signals in their respective functional groups. Table 11 briefly describes each of the MC68307 signals. CS2B/PA0 CS2C/PA1 CS2D/PA2 MULTIPLEXED TOUT1/PA3 PARALLEL I/O TOUT2/PA4 BR/PA5 BG/PA6 BGACK/PA7 AS UDS LDS ...

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Mnemonic D15-D0 Data bus A23-A8 Address bus out AD7-AD0/A7-A0 Multiplexed 8051 address/data/Address bus out AS Address strobe UDS Upper data strobe LDS Lower data strobe R/W Read/write DTACK Data acknowledge HALT System halt RESET System reset TRST/RSTIN Power-on reset CS0 ...

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ELECTRICAL CHARACTERISTICS PRELIMINARY DC ELECTRICAL SPECIFICATIONS Characteristic Input high voltage (except clock) Input low voltage Clock input high voltage Input leakage current @5.25V (all input-only pins) Three-state (off state) input current @2.4V/0.4V Output high voltage (I = rated maximum) OH ...

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DRIVE TO 2.4 V CLK DRIVE TO 0 2.0 V OUTPUTS (1) CLK VALID OUTPUT n 0.8 V OUTPUTS (2) CLK DRIVE TO 2.4 V INPUTS (3) CLK DRIVE TO 0.5 V INPUTS (4) CLK ALL SIGNALS (5) ...

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PRELIMINARY AC ELECTRICAL SPECIFICATIONS—CONTROL TIMING (See Figure 7) Num Frequency of operation 1 Cycle time 2,3 Clock pulse width 4,5 Clock rise and fall time 2 NOTE: Timing measurements are referenced to and from a low ...

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PRELIMINARY AC TIMING SPECIFICATIONS (V = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc Num 6 Clock low to address valid 7 Clock high to address, data bus high impedance (maximum) 8 Clock high to address (minimum) a ...

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PRELIMINARY AC TIMING SPECIFICATIONS (V = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc Num 55 R/W asserted to data bus impedance change e 56 HALT/RESET pulse width 57 BGACK negated to AS, CSx, LDS, UDS, R/W driven ...

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CLK A23–A1 CSx LDS / UDS R/W DTACK D15–D0 BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK) guarantees their recognition at the next ...

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S0 CLK A23–A1 CSx, AS (NOTE 2) LDS / UDS R/W (NOTE 2) 13 DTACK D15–D0 BR (NOTE 3) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK) guarantees ...

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CLK Strobes and R/W BR BGACK 35 BG PRELIMINARY 8051 BUS INTERFACE MODULE AC ELECTRICAL SPECIFICATIONS (V = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc Symbol Characteristic t Cycle time cyc TLHLL ALE pulse width TAVLL Address ...

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ALE RD AD7 – AD0 A23–A8 Figure 11. External Dat3a Memory Read Cycle ALE WR TAVLL AD7–AD0 A23–A8 Figure 12. External Data Memory Write Cycle MOTOROLA TLHLL TLLDV TLLWL TRLRH TLLAX TRLDV TAVLL Address TRLAZ TAVWL TAVDV TLHLL TLLWL TWLWH ...

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PRELIMINARY IEEE 1149.1 ELECTRICAL SPECIFICATIONS (V = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc Num Characteristic TCK frequency of operation 1 TCK cycle time 2 TCK clock pulse width measured at 1 TCK rise and ...

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TCLK TDI TMS TDO TDO TDO Figure 15. Test Access Port Timing Diagram PRELIMINARY TIMER MODULE ELECTRICAL SPECIFICATIONS (V = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc Num Characteristic 1 Timer input capture pulse width 2 TINclock ...

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PRELIMINARY UART ELECTRICAL SPECIFICATIONS (V = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc Num Characteristic 1 TxD output valid from TxC low 2 RxD data setup time to RxC high 3 RxD data hold time from RxC ...

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PRELIMINARY M-BUS INTERFACE INPUT SIGNAL TIMING (V = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc Num Characteristic 1 Start condition hold time 2 Clock low period 3 SDA/SCL rise time 4 Data hold time 5 SDA/SCL fall ...

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The MC68307 is available in a 100-lead QFP package (FG suffix). Figure 20 shows the MC68307 pinout. Figure 21 shows the case drawing for the MC68307 TMS D15 D14 D13 D12 GND D11 D10 ...

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MC68307FG CASE 842B-01 0. – BASE METAL DETAIL "A" SEATING H PLANE MILLIMETERS INCHES DIM MIN MAX MIN A 19.90 ...

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The documents listed in the following table contain detailed information on the MC68307. These documents may be obtained from the Literature Distribution Centers at the addresses listed below. Document Title M68300 Integrated Processor Family MC68307 User's Manual M68000 Family Programmer's ...

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