mc68341umad Freescale Semiconductor, Inc, mc68341umad Datasheet

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mc68341umad

Manufacturer Part Number
mc68341umad
Description
Integrated Processor Users Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Parts Not Suitable for New Designs
For Additional Information
End-Of-Life Product Change Notice

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mc68341umad Summary of contents

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Parts Not Suitable for New Designs For Additional Information End-Of-Life Product Change Notice ...

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... LPSTOP broadcast access to $3FFFE. The remaining address range $3FF04-3FFFD is Motorola reserved and should not be accessed. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. SEMICONDUCTOR PRODUCT INFORMATION MOTOROLA, 1995 Order this document by MC68341UMAD/AD MC68341 ...

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S0 CLKOUT A31– FC3–FC0 SIZ1 SIZ0 R/W AS CSx DS AS68K UDS, LDS UWE LWE DSACK DTC D15–D8 D7–D0 WORD WRITE Figure 3-12. M68300 Write Cycle timing MOTOROLA WORD OP2 OP3 BYTE WRITE MC68341 ...

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S0 S2 CLKOUT A31– FC3–FC0 SIZ1 SIZ0 R/W AS68K CSx DS AS UDS LDS UWE LWE DSACK DTC D15–D8 D7–D0 WORD WRITE Figure 3-14. M68000 Write Cycle Timing MOTOROLA WORD OP2 OP3 BYTE WRITE MC68341 ...

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Additional Notes on CPU Space Address Encoding On page 3-31, Figure 3-16, the BKPT field for the Breakpoint Acknowledge address encoding is on bits 4-2, and the T bit is on bit 1. The Interrupt Acknowledge LEVEL field is ...

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This can be done by asserting HALT and BERR either synchronously to the clock to directly control which edge each is recognized on, or asynchronously with HALT asserted for time [spec 47A+spec 47B] ns before BERR to ...

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VCO lock is set after completion of the 328 clock delay. For external clock mode without VCO, the 328*TCLKIN delay starts as soon as EXTAL clock transitions are recognized. See note ...

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Table 4-2. System Frequencies from 32.768-kHz Reference CLKOUT (kHz 131 4 82 164 5 98 197 ...

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Table 4-2. System Frequencies from 32.768-kHz Reference (Continued) CLKOUT (kHz 541 1081 33 557 1114 34 573 1147 35 590 1180 36 606 1212 37 623 ...

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Additional Note on PORTA/B Output Timing Add to the External Bus Interface Operation description on page 4-17: The Port A and Port B output pins tran- sition after the S4 falling edge for the internal write to the respective ...

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A VCO overshoot can occur when increasing the operating frequency by changing the Y bits in the SYNCR register. The effects of this overshoot can be controlled by following this procedure: 1. Write the X bit to zero. This will ...

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Additional Notes on DMA Features In the feature set listed on page 6-1, bullet six is “Operand Packing and Unpacking for Dual-Address Trans- fers”. This packing is for transfers between different port sizes selected in the DMA channel control ...

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Additional Note on Cycle Steal For the external cycle steal mode description on page 6-6, the initial DREQx assertion does not have to be held off until after the channel is started. If DREQx is already asserted when the ...

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Single Address Enable 6-33 SE-Single Address Enable: The note “used for intermodule DMA” should be for the SE=1 case. The 68341 does not support intermodule single address transfers, so the SE bit should always be programmed to “0”. 52. ...

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This method preserves most of the standard baud rates (19200, 9600, 4800, etc.). Serial XTAL Frequency 3.6864MHz 1.8432 0.9216 CLKOUT min = 2.25*XTAL frequency Alternatively, the baud rate clock can be supplied directly through the ...

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Timer register offsets from timer1 base address IR EQU $4 CR EQU $6 SR EQU $8 CNTR EQU $A PRLD1 EQU $C COM EQU $10 On page 8-27, change the last code line from "CLR.W SR(A0)" to "ORI.W #$7000,SR(A0)". ...

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Corrections to 8/16-Bit DMA Control Logic On page 11-10, the logic driving OE on the 74F245 in Figure 11-14 should be corrected as shown below. Al- though not detailed, the byte enables for the memory block should be controlled ...

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PLL phase locks the falling edge of CLKOUT to the falling edge on EXTCLK. 70. Data Setup Time for 3.3V On page 12-9, electrical specification #27 (Data Setup to CLKOUT Low) for 3.3V ...

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Page 6-5, Paragraph 6.3.1.2 The table reference in the last sentence should be 6-4 not 6-5. 80. Page 9-19, The timing diagrams reference as Figures 9-24 — 9-27 should be changes to 12-22–12-25. 81. Page 9-29, DT–Delay A value ...

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Y –A– –H– –C– H DETAIL C MOTOROLA L –B– DETAIL A –D– DETAIL C –H– M TOP & BOTTOM Case 864A-03 MC68341 USER’S MANUAL ADDENDUM –A–, ...

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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