mpc8555e Freescale Semiconductor, Inc, mpc8555e Datasheet
mpc8555e
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mpc8555e Summary of contents
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... PowerQUICC™ III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual. To locate any published errata or updates for this document refer to http://www ...
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... Overview 1 Overview The following section provides a high-level overview of the MPC8555E features. major functional units within the MPC8555E. DDR DDR SDRAM Controller SDRAM Controller DUART GPIO Local Bus Controller 32b Programmable IRQs Interrupt Controller CPM MPHY FCC UTOPIA FCC SCC MIIs/RMIIs ...
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... Internal timer — Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and virtual DMA channels for each peripheral controller — Handles serial protocols and virtual DMA MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Overview 3 ...
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... General-purpose parallel ports—16 parallel I/O lines with interrupt capability • 256 Kbytes of on-chip memory — Can act as a 256-Kbyte level-2 cache — Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 4 Freescale Semiconductor ...
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... Programming model is compliant with the OpenPIC architecture — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts — Supports 4 message interrupts with 32-bit messages MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Overview 5 ...
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... Two Three-speed (10/100/1000)Ethernet controllers (TSECs) — Dual IEEE 802.3, 802.3u, 802.3x, 802.3z AC compliant controllers — Support for Ethernet physical interfaces: – 10/100/1000 Mbps IEEE 802.3 GMII – 10/100 Mbps IEEE 802.3 MII MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 addressing mode 2 ...
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... Supports PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Overview 7 ...
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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8555E. The MPC8555E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. ...
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... PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation shown in Figure 3. 2.1.2 Power Sequencing The MPC8555Erequires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up DDn 2. GV ...
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... From a system standpoint, if the I/O power supplies ramp prior to the V core supply, the I/Os on the MPC8555E may drive a logic one or zero during power-up. 2.1.3 Recommended Operating Conditions Table 2 provides the recommended operating conditions for the MPC8555E ...
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... Note that t SYS Figure 2. Overshoot/Undershoot Voltage for GV The MPC8555E core voltage must always be provided at nominal 1.2 V (see recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in respect to the associated I/O supply voltage. OV circuits and satisfy appropriate LVCMOS type specifications ...
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... Electrical Characteristics Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8555E for the 3.3-V signals, respectively. Overvoltage Waveform Undervoltage Waveform Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling 2.1.4 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates ...
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... Maximum power is based on a nominal voltage artificial smoke test. 6. The nominal recommended V = 1.3V for this speed grade. DD Notes MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor (1) (2) Table 4. Power Dissipation V Typical Power DD 400 1.2 500 1.2 600 1 ...
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... RMII HDLC 16 Mbps UTOPIA-8 SPHY UTOPIA-8 MPHY UTOPIA-16 SPHY UTOPIA-16 MPHY CPM - SCC HDLC 16 Mbps TDMA or TDMB Nibble Mode TDMA or TDMB Per Channel MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 14 Table 5. Typical I/O Power Dissipation (2 ...
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... Clock Timing 4.1 System Clock Timing Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8555E. Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter Notes: 1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies ...
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... Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of HRESET Notes: 1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8555E. See the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for more details. Table 10 provides the PLL and DLL lock times ...
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... Output leakage is measured with all outputs disabled Table 12 provides the DDR capacitance. Parameter/Condition Input/output capacitance: DQ, DQS, MSYNC_IN Delta input/output capacitance: DQ, DQS Note: 1. This parameter is sampled MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Symbol Min GV 2.375 DD 0.49 × ...
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... MCK[n] cycle time, (MCK[n]/MCK[n] crossing) Skew between any MCK to ADDR/CMD ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS(n) output setup with respect to MCK MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 2.5 V ± 5%. DD Symbol ...
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... Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8555E. 7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8555E. Note that t conventions described in note 1. MPC8555E PowerQUICC™ ...
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... DDR SDRAM output timing diagram for the source synchronous mode. MCK[n] MCK[n] ADDR/CMD Write A0 t DDKHMP MDQS[n] MDQ[x] Figure 5. DDR SDRAM Output Timing Diagram for Source Synchronous Mode MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 20 MCK[n] MCK[n] t MCK t AOSKEWmax) CMD t ...
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... DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8555E. 7.1 DUART DC Electrical Characteristics Table 16 provides the DC electrical characteristics for the DUART interface of the MPC8555E. Table 16. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current ...
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... Ethernet: Three-Speed, MII Management 7.2 DUART AC Electrical Specifications Table 17 provides the AC timing parameters for the DUART interface of the MPC8555E. Parameter Minimum baud rate Maximum baud rate Oversample rate Notes: 1. Actual attainable baud rate is limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8 bit ...
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... DD 1 Input high current ( Input low current (V = GND) IN Note: 1. Note that the symbol this case, represents the LV IN MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Conditions — –4 Min 4 Min OL DD — ...
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... R (rise (fall). 2. Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3. Guaranteed by characterization. 4. Guaranteed by design. Figure 7 shows the GMII transmit AC timing diagram. GTX_CLK TXD[7:0] TX_EN TX_ER MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 3.3 V ± 5 Symbol t GTX t /t ...
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... Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3. Guaranteed by design. Figure 8 provides the AC test load for TSEC. Output Figure 9 shows the GMII receive AC timing diagram. RX_CLK RXD[7:0] RX_DV RX_ER MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 Symbol t GRX t /t GRXH ...
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... R (rise (fall). 2. Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3. Guaranteed by design. Figure 10 shows the MII transmit AC timing diagram. TX_CLK TXD[3:0] TX_EN TX_ER MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 3.3 V ± 5 Symbol 2 t MTX ...
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... R (rise (fall). 2. Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. Figure 11 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 Symbol 2 t MRX ...
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... R (rise (fall). 2. Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3. Guaranteed by design. Figure 12 shows the TBI transmit AC timing diagram. GTX_CLK TCG[9:0] MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 3.3 V ± 5 Symbol t ...
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... R (rise (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Guaranteed by design. Figure 13 shows the TBI receive AC timing diagram. RX_CLK1 RXD[9:0] RX_CLK0 MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 Symbol t TRX ...
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... Guaranteed by characterization. 6. Guaranteed by design. 7. Signal timings are measured at 0.5 and 2.0 V voltage levels. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 30 Specifications of 2.5 V ± 5%. DD ...
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... Table 27. MII Management DC Electrical Characteristics Parameter Symbol Supply voltage (3 Output high voltage V Output low voltage V Input high voltage V Input low voltage V MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] ...
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... MHz, the delay is 58 ns). 3. This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay and for a CCB clock of 333 MHz, the delay is 48 ns). 4. Guaranteed by design. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 32 Conditions 1 ...
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... High-level input voltage Low-level input voltage Input current High-level output voltage Low-level output voltage Note: 1. Note that the symbol this case, represents the OV IN MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t MDC t t MDCF MDCH t ...
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... Local Bus 9.2 Local Bus AC Electrical Specifications Table 30 describes the general timing parameters of the local bus interface of the MPC8555E with the DLL enabled. Table 30. Local Bus General Timing Parameters—DLL Enabled Parameter Local bus cycle time LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except ...
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... OV / Guaranteed by characterization. 9. Guaranteed by design. Table 31 describes the general timing parameters of the local bus interface of the MPC8555E with the DLL bypassed. Table 31. Local Bus General Timing Parameters—DLL Bypassed Parameter Local bus cycle time Internal launch/capture clock to LCLK ...
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... Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals Guaranteed by characterization. 9. Guaranteed by design. Figure 16 provides the AC test load for the local bus. Output MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 Configuration Symbol LWE[0: LBKLOV3 LWE[0: (default) ...
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... Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t LBIVKH1 t LBIVKH1 t LBKHOZ1 t t LBKHOV1 ...
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... LGTA Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 18. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 LBKHKT t LBIVKH1 t LBIVKH2 t LBKLOV1 t ...
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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 ...
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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 LBKHKT t t LBKLOX1 LBKLOV1 ...
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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t ...
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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 LBKHKT t t LBKLOX1 ...
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... CPM This section describes the DC and AC electrical specifications for the CPM of the MPC8555E. 10.1 CPM DC Electrical Characteristics Table 32 provides the DC electrical characteristics for the CPM. Characteristic Input high voltage Input low voltage Output high voltage Output low voltage Output high voltage Output low voltage Note: 1. This specification applies to the following pins: PA[0– ...
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... Figure 23 provides the AC test load for the CPM. Output MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 44 (first two letters of functional block)(signal)(state) (K) going to the high (H) state or setup time. And t (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...
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... FCC Output Signals (When GFMR TCI = 1) Figure 25. FCC External AC Timing Clock Diagram Figure 26 shows Ethernet collision timing on FCCs. COL (Input) Figure 26. Ethernet Collision AC Timing Diagram (FCC) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 33 and t FIIXKH t FIIVKH ...
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... Figure 28. SCC/SMC/SPI AC Timing Internal Clock Diagram 1 SPI AC timings are internal mode when it is master because SPICLK is an output, and external mode when it is slave. 2 SPI AC timings refer always to SPICLK MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 NEIXKH t NEKHOX ...
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... High period of SCL 2 Start condition setup time 2 Start condition hold time 2 Data hold time 2 Data setup time SDA/SCL rise time MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t TDIXKH t TDIVKH t TDKHOX Figure 29. TDM Signal AC Timing Diagram t PIIXKH PIIVKH Figure 30 ...
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... SCL In master mode: divider=BRGCLK/(f In slave mode: divider=BRGCLK/(f SDA t t SCLCH SDHDL t SCHDL SCL t SDLCL MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 48 Table 35. I2C Timing (continued) Expression Min t - SFALL t 2/(divider * f SCHDH *prescaler)=2*(I2BRG[DIV]+3) SCL *prescaler) SCL ...
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... Start condition setup time Start condition hold time Data hold time Data setup time SDA/SCL rise time SDA/SCL fall time Stop condition setup time MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 36. CPM I2C Timing (f =100 kHz) SCL Expression f ...
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... TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 50 Table 2). ...
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... Figure 32 provides the AC test load for TDO and the boundary-scan outputs of the MPC8555E. Output Figure 32. AC Test Load for the JTAG Interface Figure 33 provides the JTAG clock input timing diagram. JTAG External Clock Figure 33. JTAG Clock Input Timing Diagram Figure 34 provides the TRST timing diagram. ...
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... C = capacitance of one bus line in pF Refer to the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for information on the digital filter used. 4. I/O pins obstruct the SDA and SCL lines if OV MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 ...
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... For rise and fall times, the latter convention is used I2C with the appropriate letter: R (rise (fall). 2. MPC8555E provides a hold time of at least 300 ns for the SDA signal (referred to the V undefined region of the falling edge of SCL. 3. The maximum t ...
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... I2CF t I2CL SCL t I2SXKL S 13 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8555E. 13.1 PCI DC Electrical Characteristics Table 41 provides the DC electrical characteristics for the PCI interface of the MPC8555E. Table 41. PCI DC Electrical Characteristics Parameter High-level input voltage ...
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... PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the MPC8555E. Note that the SYSCLK signal is used as the PCI input clock. MHz. PCI Clock can be PCI1_CLK or SYSCLK based on POR config input. The input setup time does not meet the PCI specification. ...
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... The package parameters are as provided in the following list. The package type × 29 mm, 783 flip chip plastic ball grid array (FC-PBGA). Die size Package outline Interconnects Pitch Minimum module height 3.07 mm Maximum module height 3.75 mm Solder Balls Ball diameter (typical) MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 PCIVKH CLK t PCKHOV t PCKHOZ Output 8.7 mm × ...
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... Mechanical Dimensions of the FC-PBGA Figure 42 the mechanical dimensions and bottom surface nomenclature of the MPC8555E 783 FC-PBGA package. Figure 42. Mechanical Dimensions and Bottom Surface Nomenclature of the FC-PBGA Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. ...
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... Package and Pin Listings 14.3 Pinout Listings Table 43 provides the pin-out listing for the MPC8555E, 783 FC-PBGA package. Signal PCI1_AD[63:32], AA14, AB14, AC14, AD14, AE14, AF14, AG14, AH14, PCI2_AD[31:0] V15, W15, Y15, AA15, AB15, AC15, AD15, AG15, AH15, V16, W16, AB16, AC16, AD16, AE16, AF16, ...
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... N19, B21, F21, K21, M21, C23, A23, B24, H23, G24, MWE MRAS MCAS MCS[0:3] MCKE[0:1] MCK[0:5] MCK[0:5] MSYNC_IN MSYNC_OUT LA[27] MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number AD18, AE18, AE19, AD19 AC22 AD20 AC20 AD21 AE21, AD22, AE22, AC23 AE20 AC21 ...
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... LWE[0:1]/LSDDQM[0:1]/ LBS[0:1] LWE[2:3]/LSDDQM[2:3]/ LBS[2:3] DMA_DREQ[0:1] DMA_DACK[0:1] DMA_DDONE[0:1] MCP UDE MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 60 Package Pin Number T18, T19, T20, T21 P18, N22, N23, N24, N25, N26 V21 V20 U23 U27, U28, V18 Y27, Y28, W27, W28, R27 ...
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... TSEC1_RXD[7:0] TSEC1_RX_DV TSEC1_RX_ER TSEC1_RX_CLK Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_TXD[7:4] TSEC2_TXD[3:0] TSEC2_TX_EN TSEC2_TX_ER TSEC2_TX_CLK TSEC2_GTX_CLK MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number AB20 Y20 AF26 AH24 AB21 Ethernet Management Interface F1 E1 Gigabit Reference Clock ...
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... HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT TRIG_IN TRIG_OUT/READY MSRCID[0:1] MSRCID[2:3] MSRCID4 MDVAL SYSCLK RTC CLK_OUT MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 62 Package Pin Number D9 F8 F9, E9, C9, B9, A9, H9, G10, F10 H8 A8 E10 DUART Y2, Y3 Y1, AD1 P11, AD5 N6, AD2 ...
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... THERM0 THERM1 ASLEEP MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number JTAG AF21 AG21 AF19 AF23 AG23 DFT AG19 AB22 AG22 AH20 AG26 Thermal Management AG2 AH3 ...
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... M13, M15, M17, N14, N16, P13, P15, P17, R12, R14, DD PA[8:31] J7, J8, K8, K7, K6, K3, K2, K1, L1, L2, L3, L4, L5, L8, L9, L10, L11, M10, M9, M8, M7, M6, M3, M2 MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 64 Package Pin Number AF10, AF13, AF15, AF27, AG3, AG7 N21 ...
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... TEST_SEL0 must be pulled-high, TEST_SEL1 must be tied to ground. 4. This pin is an open drain signal. 5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8555E is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor external device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is intended to be high during reset ...
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... Clocking 15 Clocking This section describes the PLL configuration of the MPC8555E. Note that the platform clock is identical to the CCB clock. 15.1 Clock Ranges Table 44 provides the clocking specifications for the processor core and specifications for the memory bus. Table 44. Processor Core Clocking Specifications ...
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... There is no default for this PLL ratio; these signals must be pulled to the desired values. For specifications on the PCI_CLK, refer to the PCI 2.2 Specification. Binary Value of LA[28:31] Signals MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 46. Table 46. CCB Clock Ratio ...
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... Table 48. Frequency Options with Respect to Memory Bus Speeds CCB to SYSCLK Ratio 200 16 267 MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 68 Table 47. e500 Core to CCB Ratio Ratio Description 00 2:1 e500 core:CCB 01 5:2 e500 core:CCB 10 3:1 e500 core:CCB 11 7:2 e500 core:CCB SYSCLK (MHz ...
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... The recommended attachment method to the heat sink is illustrated in board with the spring force centered over the die. This spring force should not exceed 10 pounds force. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 49. Package Thermal Characteristics Figure 43 ...
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... Thermal Thermal Interface Material Figure 43. Package Exploded Cross-Sectional View with Several Heat Sink Options The system board designer can choose between several types of heat sinks to place on the MPC8555E. There are several commercially-available heat sinks from the following vendors: Aavid Thermalloy 80 Commercial St. ...
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... MPC8555E to function in various environments. 16.2.1 Recommended Thermal Model For system thermal modeling, the MPC8555E thermal model is shown in to represent this device. To simplify the model, the solder balls and substrate are modeled as a single block 29x29x1.6 mm with the conductivity adjusted accordingly. The die is modeled as 8 thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed resistance between the die and substrate assuming a conductivity of 4.4 W/m• ...
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... When removing the heat sink for re-work preferable to slide the heat sink off slowly until the thermal interface material loses its grip. If the support fixture around the package prevents sliding off the heat sink, MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 72 ...
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... Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company th 18930 West 78 St. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease 20 ...
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... Assuming an air velocity of 2 m/s, we have an effective θ = 30°C + 5°C + (0.96°C/W + 3.3°C/W) × 8 resulting in a die-junction temperature of approximately 69°C which is well within the maximum operating temperature of the component. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 74 888-246-9050 + θ + θ ) × P ...
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... For applications with significant vibration requirements, silicone damping material can be applied between the heat sink and plastic frame. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Thermalloy #2328B Pin-fin Heat Sink (25 × 28 × 15 mm) ...
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... Figure 48 and provide exploded views of the plastic fence, heat sink, and spring clip. Figure 48. Exploded Views ( Heat Sink Attachment using a Plastic Fence MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 76 Freescale Semiconductor ...
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... For these reasons, we recommend using conjugate heat transfer models for the boards, as well as, system-level designs. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Thermal ...
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... Each circuit should be placed as close as possible to the specific AV noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 ...
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... Decoupling Recommendations Due to large address and data buses, and high operating frequencies, the MPC8555E can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8555E system, and the MPC8555E itself requires a clean, tightly regulated source of power ...
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... DD Local Bus, Ethernet, DUART, Control, Configuration, Power Impedance Differential Note: Nominal supply voltages. See MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 trimmed until the voltage at the pad equals P )/ Pad Data ...
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... Configuration Pin Multiplexing The MPC8555E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. ...
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... IC). Regardless of the numbering, the signal placement recommended in all known emulators. COP_SRESET COP_HRESET COP_CHKSTP_OUT MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 82 allows the COP port to independently assert HRESET or TRST, Figure 52, for connection to the target system, and is 2 ...
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... Tie TCK to OV through a 10 kΩ resistor. This prevents TCK from changing state and reading DD incorrect data into the device. • No connection is required for TDI, TMS, or TDO. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor System Design Information 83 ...
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... This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed. 6. Asserting SRESET causes a machine check interrupt to the e500 core. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 84 COP_HRESET ...
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... Corrected symbols for body rows 9–15, effectively changing them from a high state to a low state in Table 0 6/2005 Initial release. MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 51. Document Revision History Substantive Change(s) Figure 3, ““Maximum AC Waveforms on PCI interface for 3.3-V Signaling.” ...
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... Nomenclature of Parts Fully Addressed by this Document Table 52 provides the Freescale part numbering nomenclature for the MPC8555E. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions ...
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... CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. Figure 54. Part Marking for FC-PBGA Device MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Figure 54 ...
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... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8555EEC Rev. 4.2 1/2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...