mpc5566 Freescale Semiconductor, Inc, mpc5566 Datasheet - Page 60

• Manufacturer Part Number: mpc5566
• Description: Mpc5566 High Performance Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Revision History for the MPC5566 Data Sheet
60
Location
Table
Figure
Table
Table
Table
9, DC Electrical Specifications (continued)
12, FMPLL Electrical Characteristics:
13, eQADC Conversion Specifications:
14, Flash Program and Erase Specifications:
3, Added figure to show interpolated IDD
• Spec 27e, Operating current 1.5 V supplies @ 147 MHz:
• Spec 28: Changed 132 MHz to f
• Spec 29: Deleted @ 132 MHz.
• Corrected footnote 3 to read: If standby operation is not required, connect the V
• Combined old footnotes 11 and 12 for new footnote 6 and added to specs 27a, b, and c on the 8-way cache line
• Deleted footnotes 12 and 13 about preliminary specifications and specification pending characterization.
• Added (T
• Spec 1, footnote 1 in column 2: ‘PLL reference frequency range’: Changed to read ‘Nominal crystal and external
• Specs 12 and 13: Grouped (2 x Cl).
• Spec 21, column 2: Changed f
• Spec 21, column 4, Max: Deleted old footnote 18 that reads:
• Spec 21: Changed column 5 from ‘f
• Spec 22: Changed column 4, Max Value from f
Added (T
• Added (T
• Specs 7, 8, 9, and 10 Inserted new values for the H7Fa Flash pre-program and erase times and used the previous
• Spec 8, 128KB block pre-program and erase time, Max column value from 15,000 to 7,500.
• Moved footnote 1 from the table title to directly after the ‘Typical’ in the column 5 header.
• Footnote 2: Changed from: ‘Initial factory condition: ≤ 100 program/erase cycles, 25
that reads: Eight-way cache enabled (L1CSR0[CORG] = 0b0).
reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within
± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.‘
added the same equation but substituted f
f
f
The ICO frequency can be higher than the maximum allowable system frequency. For this case, set the CMPLL
synthesizer control register reduced frequency divider (FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001).
Therefore, for a 40 MHz maximum device (system frequency), program the FMPLL to generate 80 MHz at the
ICO output and then divide-by-two the RFD to provide the 40 MHz system clock.’
dual controller (1:1) mode is (f
values for Typical values.
80 MHz minimum system frequency.‘ To: ‘Initial factory condition: ≤ 100 program/erase cycles, 25
typical supply voltage measured at a minimum system frequency of 80 MHz.’
Added 4-way cache: all with footnote 11.
Added maximum values for 8-way cache: all with footnote 11.
•
•
•
•
•
•
ico
ico
•
•
Table 33. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued)
= [ f
= [ f
1.65 typical = 650,
1.35 typical = 530,
1.65 high = 820,
1.35 high = 650.
1.65 high = 720
1.35 high = 585
48 KB: from 340 to 345
64 KB: from 400 to 415
A
ref_crystal
ref_ext
= T
A
A
= T
= T
L
× (MFD + 4) ] ÷ (PREDIV + 1)
– T
L
L
– T
– T
× (MFD + 4) ] ÷ (PREDIV + 1)
H
) to the table title.
H
H
) to the end of the second line in the table title.
) to the table title.
MPC5566 Microcontroller Data Sheet, Rev. 2.0
MAX
ref_crystal
MAX
STBY
÷ 2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’
SYS
MHz.
values listed in
’ MHz’ to: ‘f
to f
Description of Changes
ref_ext
ref
in ICO frequency equation, and
MAX
for f
MAX
to 20, and added footnote 17 to read, ‘Maximum value for
ref
Table
’.
for the external reference clock, giving:
9.
STBY
o
to ground.
C, typical supply voltage,
Freescale Semiconductor
o
C, using a