dp83950b National Semiconductor Corporation, dp83950b Datasheet - Page 19

• Manufacturer Part Number: dp83950b
• Description: Dp83950b Rictm Repeater Interface Controller
• Manufacturer: National Semiconductor Corporation

Pin
No
PROCESSOR BUS PINS
3 0 Pin Descriptions
RA0 – RA4
MLOAD
BUFEN
D0 – D7
Name
CDEC
STR0
STR1
RDY
RTI
WR
Pin
ELI
RD
Driver
Type
TT
TT
TT
TT
TT
TT
C
C
C
C
C
C
B Z
I O
O
O
O
O
O
O
I
I
I
I
I
(Continued)
REGISTER ADDRESS INPUTS These five pins are used to select a register to be read or
written The state of these inputs are ignored when the read write and mode load input strobes
are high (Even under these conditions these inputs must not be allowed to float at an
undefined logic state)
DISPLAY UPDATE STROBE 0
Maximum Display Mode This signal controls the latching of display data for network ports 1
to 7 into the off chip display latches
Minimum Display Mode This signal controls the latching of display data for the RIC into the
off chip display latch
During processor access cycles (read or write is asserted) this signal is inactive (high)
DISPLAY UPDATE STROBE 1
Maximum Display Mode This signal controls the latching of display data for network ports 8
to 13 into the off chip display latches
Minimum Display Mode No operation
During processor access cycles (read or write is asserted) this signal is inactive (high)
DATA BUS
Display Update Cycles These pins become outputs providing display data and port address
information Address information only available in Maximum Display mode
Processor Access Cycles Data input or output is performed via these pins The read write
and mode load inputs control the direction of the signals
Note The data pins remain in their display update function i e asserted as outputs unless either the read or
write strobe is asserted
BUFFER ENABLE This output controls the TRI-STATE operation of the bus transceiver
which provides the interface between the RIC’s data pins and the processor’s data bus
Note The buffer enable output indicates the function of the data pins When it is high they are performing
display update cycles when it is low a processor access or mode load cycle is occurring
DATA READY STROBE The falling edge of this signal during a read cycle indicates that data
is stable and valid for sampling In write cycles the falling edge of RDY denotes that the write
data has been latched by the RIC Therefore data must have been available and stable for this
operation to be successful
EVENT LOGGING INTERRUPT A low level on the ELI output indicates the RIC’s hub
management logic requires CPU attention The interrupt is cleared by accessing the Port Event
Recording register or Event Counter that produced it All interrupt sources may be masked
REAL TIME INTERRUPT A low level on the RTI output indicates the RIC’s real time (packet
specific) interrupt logic requires CPU attention The interrupt is cleared by reading the Real
Time Interrupt Status register All interrupt sources may be masked
COUNTER DECREMENT A low level on the CDEC input strobe decrements all of the RIC’s
Port Event Counters by one This input is internally synchronized and if necessary the
operation of the signal is delayed if there is a simultaneous internally generated counting
operation
WRITE STROBE Strobe from the CPU used to write an internal register defined by the
RA0 – RA4 inputs
READ STROBE Strobe from the CPU used to read an internal register defined by the RA0 –
RA4 inputs
DEVICE RESET AND MODE LOAD When this input is low all of the RIC’s state machines
counters and network ports are reset and held inactive On the rising edge of MLOAD the logic
levels present on the D0 – 7 pins and RA0 – RA4 inputs are latched into the RIC’s configuration
registers The rising edge of MLOAD also signals the beginning of the display test operation
19
Description