dp83950b National Semiconductor Corporation, dp83950b Datasheet - Page 44

• Manufacturer Part Number: dp83950b
• Description: Dp83950b Rictm Repeater Interface Controller
• Manufacturer: National Semiconductor Corporation

6 0 Hub Management Support
Each counter is 16 bits long and may be directly read by the
processor Additionally each counter has a number of de-
codes to indicate the current value of the count There are
three decodes
The decodes from each counter are logically ‘‘ORed’’ to-
gether and may be used as interrupt sources for the ELI
interrupt pin Additionally the status of these bits may be
observed by reading the Page Select Register (PSR) (see
Section 8 for register details) In order to enable any of
these threshold interrupts the appropriate interrupt mask bit
must be written to the Management and Interrupt Configura-
tion Register see Section 8 for register details
In addition to their event masking functions the Upper Event
Counting Mask Register (UECMR) possesses two bits
which control the operation of the counters When written to
a logic one the reset on read bit ‘‘ROR’’ resets the counter
after a processor read cycle is performed If this operation is
not selected then in order to zero the counters they must
either be written with zeros by the processor or allowed to
roll over to all zeros The freeze when full bit ‘‘FWF’’ pre-
vents counter roll over by inhibiting count up cycles (these
happen when chosen events occur) thus freezing the par-
ticular counter at FFFF Hex
The port event counters may also be controlled by the
Counter Decrement (CDEC) pin As its name suggests a
logic low state on this pin will decrement all the counters by
a single value The pulses on CDEC are internally synchro-
nized and scheduled so as not to conflict with any ‘‘up
counting’’ activity If an up count and a down count occur
simultaneously then the down count is delayed until the up
count has completed This combination of up and down
counting capability enables the RIC’s on-chip counters to
provide a simple rolling average or be used as extensions of
larger off chip counters
Note If the FWF option is enabled then the count down operation is dis-
Reading the Event Counters
The RIC’s external data bus is eight bits wide since the
event counters are 16 bits long two processor read cycles
are required to yield the counter value In order to ensure
that the read value is correct and to allow simultaneous
event counts with processor accesses a temporary holding
register is employed A read cycle to either the lower or
upper byte of a counter causes both bytes to be latched
into the holding register Thus when the other byte of the
counter is obtained the holding register is accessed and not
the actual counter register This ensures that the upper and
lower bytes contain the value sampled at the same instance
in time i e when the first read cycle to that counter oc-
curred
There is no restriction concerning whether the upper or low-
er byte is read first However to ensure the ‘‘same instance
value’’ is obtained the reads of the upper then lower byte
(or vice versa) should be performed as consecutive reads of
Low Count (a value of 00FF Hex and under)
High Count (a value of C000 Hex and above)
Full Count (a value of FFFF Hex)
abled from those registers which have reached FFFF Hex and conse-
quently have been frozen Thus if FWF is set and CDEC has been
employed to provide a rate indication A frozen counter indicates that
a rate has been detected which has gone out of bounds i e too fast
increment or too slow increment If the low count and high count
decodes are employed as either interrupt sources or in a polling cycle
the direction of the rate excursion may be determined
(Continued)
44
the counter array Other NON COUNTER registers may be
read in between these read cycles and also write cycles
may be performed If another counter is read or the same
byte of the original counter is read then the holding register
is updated from the counter array and the unread byte is
lost
If the reset on read option is employed then the counter is
reset after the transfer to the holding register is performed
Processor read and write cycles are scheduled in such a
manner that they do not conflict with count up or count
down operations That is to say in the case of a processor
read the count value is stable when it is loaded into the
holding register In the case of a processor write the newly
written value is stable so it maybe incremented or decre-
ment by any subsequent count operation During the period
the MLOAD pin is low (power on reset) all counters are
reset to zero and all count masks are forced into the dis-
abled state Section 8 of the data sheet details the address
location of the port event counters
6 2 EVENT RECORD FUNCTION
As previously stated each repeater port has its own Event
Recording Register This is an 8-bit status register each bit
is dedicated to logging the occurrence of a particular event
(see Section 8 for detailed description) The logging of
these events is controlled by the Event Recording Mask
Register for an event to be recorded the particular mask bit
must be set (see Section 8 description of this register) Sim-
ilar to the scheme employed for the event counters the
recorded events are latched during the repetition of a pack-
et and then automatically loaded into the recording registers
at the end of transmission of a packet When one of the
unmasked events occurs the particular port register bit is
set This status is visible to the user All of the register bits
for all of the ports are logically ‘‘ORed’’ together to produce
a Flag Found ‘‘FF’’ signal This indicator may be found by
reading the Page Select Register Additionally an interrupt
may be generated if the appropriate mask bit is enabled in
the Management and Interrupt Configuration Register
A processor read cycle to a Event Record Register resets
any of the bits set in that register Read operations are
scheduled to guarantee non changing data during a read
cycle Any internal bit setting event which immediately fol-
lows a processor read will be successful The events which
may be recorded are described below
Jabber Protection (JAB) This flag goes active if the length
of a received packet from the relevant port causes the re-
peater state machine to enter the Jabber Protect state
Elasticity Buffer Error (ELBER) This condition occurs if
an Elasticity Buffer full or overflow occurs during packet re-
ception The flag is held inactive if a collision occurs during
packet reception or if a phase lock error has already oc-
curred during the repetition of the packet
Phase Lock Error (PLER) A phase lock error is caused if
the phase lock loop decoder loses lock during packet re-
ception Phase lock onto the received data stream may or
may not be recovered later in the packet and data errors
may have occurred This flag is held inactive if a collision
occurs
Non SFD Packet (NSFD) If a packet is received and the
start of frame delimiter is not found the flag will go active
The flag is held inactive if a collision occurs in during packet
repetition