w682510 Winbond Electronics Corp America, w682510 Datasheet
w682510
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w682510 Summary of contents
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... W682510/W682310 DUAL-CHANNEL VOICEBAND CODECS ADVANCED Publication Release Date: April 2005 - 1 - Revision A10 ...
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... The W682510 and W682310 are general-purpose dual channel PCM CODECs with pin-selectable μ- Law or A-Law companding. The device is compliant with the ITU G.712 specification. It operates from a single power supply (+5V for the W682510, +3V for the W682310) and is available in 20-pin PDIP (W682510 only), SSOP, and 24-pin SOP package options. Functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems ...
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... PCMR1 PCMR1 PCMR2 PCMR2 DATA T1 DATA T1 DATA R1 DATA R1 DATA T2 DATA T2 DATA R2 DATA R2 PLL PLL Power Conditioning Power Conditioning Power Conditioning - 3 - W682510/W682310 μ /A-Law μ /A-Law RO1 RO1 RO1 AO1 - AO1 - AO1 - CODEC CODEC AI1 AI1 AI1 Filter 1 Filter 1 μ μ /A -Law /A -Law μ ...
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... Power Signals .......................................................................................................................... 11 7.3.1. V ........................................................................................................................................ 11 DD 7.3.2. V ...................................................................................................................................... 11 SSA 7.3.3. V ...................................................................................................................................... 11 SSD 7.3.4. V ...................................................................................................................................... 12 REF 7.3.5. PUI ....................................................................................................................................... 12 7.4. PCM Interface .......................................................................................................................... 12 7.4.1. μ/A-Law ................................................................................................................................ 12 7.4.2. BCLK .................................................................................................................................... 13 7.4.3. FSR ...................................................................................................................................... 13 7.4.4. FST....................................................................................................................................... 13 7.4.5. PCMMS ................................................................................................................................ 13 7.5. Power State Modes ................................................................................................................. 13 7.5.1. Power Save Mode................................................................................................................ 13 7.5.2. Power Down Mode............................................................................................................... 14 7.5.3. Power Save/Down Output pin state ..................................................................................... 14 8. TIMING DIAGRAMS ......................................................................................................................... 15 9. ABSOLUTE MAXIMUM RATINGS................................................................................................... 19 W682510/W682310 - 4 - ...
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... Analog Input and Output Amplifier Parameters 10.6. Digital I/O ................................................................................................................................ 26 11. TYPICAL APPLICATION CIRCUIT................................................................................................ 29 12. PACKAGE DRAWING AND DIMENSIONS................................................................................... 31 12.1. 20L (PDIP) Plastic Dual Inline Package Dimensions (W682510 only) 12.2. 20L SSOP – 209 mil Shrink Small Outline Package Dimensions 12.3. 24 SOP – 300 mil .................................................................................................................. 33 13. ORDERING INFORMATION .......................................................................................................... 34 14 ...
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... SOP W682510 W682310 6 15 DUAL 7 14 CHANNEL 8 13 CODEC PDIP (W682510 only), SSOP - 6 - W682510/W682310 AI2 AO2 - AO1 - AI1 NC μ/ A- Law V SSA NC BCLK FST PCMT2 PCMT1 AI2 AI2 AO2 - AO2 - AO1 - AO1 - AI1 AI1 μ/ ...
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... RO2 2 2 CH2 Non-Inverting output of the receive smoothing filter. This pin can typically drive a 600 Ω load (W682510) or 1200 Ω load (W682310). RO1 3 4 CH1 Non-Inverting output of the receive smoothing filter. This pin can typically drive a 600 Ω load (W682510) or 1200 Ω load (W682310).. ...
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... A-Law companders. The μ-Law and A-Law companders are designed to comply with the specifications of the ITU-T G.711 recommendation. The block diagram in section 3 shows the main components of the W682510/W682310. The chip consists of a PCM interface, which can process the data in parallel or serial formats. The PLL of the chip provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync frequency ...
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... AO2- AO2- AO2- AO2- AI2 AI2 AI2 AI2 - - - - + + + + - 9 - W682510/W682310 on the W682510 or are high SSA Gain=R2/R1 ≤ 10 Gain=R2/R1 ≤ > Ohm R2 > Ohm Gain=R4/R3 ≤ 10 Gain=R4/R3 ≤ > Ohm R4 > Ohm Publication Release Date: April 2005 Revision A10 ...
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... When the digital PCM signal of +3 dBm0 is presented to PCMR1 or PCMR2, it can drive a load REF of 600 Ohms or more supply voltage for the W682510 and 1200 Ohms at 3V supply for the W682310. During power saving mode, these outputs are at the voltage level of V impedance. These outputs have a feature that reduces audio “ ...
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... IGNALS 7.3. The power supply for the analog and digital parts of the W682510 must be 5V +/- 10% and 2.7V to 3.8V for the W682310. This supply voltage is connected to the V decoupled to ground through a 0.1 μF ceramic capacitor. A power supply for an analog circuit in the system to which the device is applied should be used. A bypass capacitor of 0.1 µ µF with good high-frequency characteristics (Low ESR) and a capacitor of 10 µ ...
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... Data Available CH1 data on PCMT1 & PCMR1 CH2 data on PCMT2 and PCMR2 (same timing as CH1) CH1 data followed by CH2 receive data on PCMR2 (total 16 bits) CH1 data followed by CH2 transmit data on PCMT1 (total 16 bits Floating W682510/W682310 Format A-Law μ -Law SSA ...
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... PLL to lock. In addition to the PLL lock-in time, the analog outputs will be set to the internal signal ground for 1 millisecond. This will avoid power up glitches at the outputs. The digital open drain outputs will remain at high impedance during this power up delay. W682510/W682310 Publication Release Date: April 2005 - 13 - ...
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... Power Save/Down Output pin state The following table shows the states of the output pins in the power save or power down mode. Product Name W682510 W682310 TABLE 7.5: OUTPUT PIN STATES Output Pin AO1-, A02- RO1, RO2 V Signal Ground SSA High Z Signal Ground - 14 - W682510/W682310 ...
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... Figure 8-2b. Receive Side Parallel Mode Timing (PCMMS=1) FIGURE 8.2: PARALLEL MODE PCM TIMING MSB Channel 2 Transmit PCM Data MSB Channel 2 Receive PCM Data W682510/W682310 Publication Release Date: April 2005 Revision A10 ...
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... BCLK FST FSR PCMTx MSB PCMRx Figure 8-3b. Burst Mode with Parallel Timing (PCMMS=1) FIGURE 8.3: BURST MODE PCM TIMING MSB Channel 2 PCM Data W682510/W682310 ...
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... Ir BCLK 1 2 FSR t FST FIGURE 8.4: PCM SYNCHRONIZATION PARAMETERS T =1/f D BCLK BCLK =1 W682510/W682310 MIN TYP MAX UNIT 8 --- KHz --- 1 --- 7 T BCLK 0 --- 500 nsec 64, 128, 256, 512, kHz 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 ...
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... SX XD2 Figure 8-5a. Transmit Timing Figure 8-5b. Receive Timing - 18 - W682510/W682310 TYP MAX UNIT MIN T --- 100 sec BCLK µ 100 --- --- nsec 100 --- --- nsec 20 --- 200 nsec 20 --- 200 nsec 20 --- 200 nsec 20 --- ...
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... SS Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. conditions. TABLE 9.2: OPERATING CONDITIONS (PACKAGED PARTS) Condition Industrial operating temperature Supply voltage (V ) W682510 5V DD Supply voltage (V ) W682310 3V DD Ground voltage ( W682510/W682310 ...
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... PCMT1, PCMT2 OL Low Voltage V Current (Operating ADC + DAC I V Current (Standby Current (Power Down Input Low Leakage Current IL W682510 4.5V – 5.5V Conditions >500 Ω Output R pullup No Load, No Signal FST or BCLK =OFF; PUI=V PUI <V < <V < < ...
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... All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. Conditions V <V < <PCMT<V Output SS DD High Z State Output PCMT1, PCMT2 = High 3 W682510/W682310 (4) (3) (4) Min Typ Max 2 +/- Publication Release Date: April 2005 Revision A10 Units μA μ ...
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... W682310 3V Reference Level T 1020 Hz 0TLP Out W682310 3V 3.17 dBm0 for μ-Law Max. Transmit T XMAX Level In 3.14 dBm0 for A-Law W682510 5V 3.17 dBm0 for μ-Law Max. Transmit T XMAX Level In 3.14 dBm0 for A-Law W682310 3V Absolute Gain G 0 dBm0 @ 1020 Hz; ABS (0 dBm0 @ T =+25° ...
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... Gain Variation –40 dBm0 LT vs. Level Tone -40 to –50 dBm0 (1020 Hz -50 to –55 dBm0 relative to –10 dBm0) W682510/W682310 --- -0.3 +0.3 --- -0.5 +0.5 --- -1.2 +1.2 Publication Release Date: April 2005 - 23 - -0.3 +0.3 DB -0.5 +0.5 -1.2 +1.2 Revision A10 ...
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... A D NALOG ISTORTION AND =5V ±10%; V W682510 W682310: V =2.7V to 3.8V PARAMETER SYM. Total Distortion vs. D LTμ Level Tone (1020 Hz, μ-Law, C-Message Weighted) Total Distortion vs. D LTA Level Tone (1020 Hz, A-Law, Psophometric Weighted) Spurious Out-Of-Band D SPO at RO- (300 Hz to 3400 Hz @ 0dBm0) ...
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... A I NALOG NPUT AND =5V ±10%; V W682510 W682310: V =2.7V to 3.8V PARAMETER AI1, AI2 Input Offset Voltage AI1, AI2 Input Resistance AO1-, AO2- Output Amplitude AO1-, AO2- Load Resistance AO1-, AO2- Load Capacitance RO1, RO2 Load Resistance RO1, RO2 Load Capacitance RO1, RO2 Output Amplitude ...
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... D4 D3 Chord Chord Step Step W682510/W682310 Normalized Decode Levels Step Step 8031 4191 2079 1023 495 231 ...
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... Digital code includes inversion of all even number bits Digital Code Chord Chord Step Step W682510/W682310 Normalized Decode Levels Step Step 4032 2112 1056 528 264 132 1 ...
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... Step bits Sign bit (D3,D2,D1,D0) 001 1110 000 1011 000 1011 001 1110 001 1110 000 1011 000 1011 001 1110 - 28 - W682510/W682310 A-Law Chord bits Step bits (D7) (D6,D5,D4) (D3,D2,D1,D0) 1 010 1010 1 101 0101 0 101 0101 0 010 1010 A-Law Chord bits Step bits ...
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... SSA BCLK 16 SSD 10 FSR FST 15 11 PCMR2 PCMT2 14 12 PCMR1 PCMT1 13 PCMT1 13 SOP - 29 - W682510/W682310 Channe Analog Input Channe Analog Input Bit Clock Input PCM 2 Ch. Serial Output Ω Publication Release Date: April 2005 Revision A10 ...
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... Channel 2 Analog Output Channel 1 Analog Output μ PCM Ch2 Serial Input PCM Ch1 Serial Input Frame Sync Input FIGURE 11.2: APPLICATION CIRCUIT FOR PARALLEL MODE OPERATION W682510/W682310 W682510/W682310 1 VREF AI2 24 2 RO2 AO2 - AO1 - 22 4 RO1 AI1 21 5 PUI μ ...
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... W682510/W682310 (W682510 ) ONLY E Base Seating e á A DIMENSION (INCH) NOM. MAX 0.175 - - 0.130 0.135 0.018 0.022 0.060 0.064 0.010 0.014 - 1.026 1.046 0.300 0.310 0.250 0.255 0.100 0.110 0.130 0.140 - 15º ...
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... DIMENSION (INCH) NOM. MAX. MIN 0.002 1.75 1.85 0.065 - 0.38 0.009 - 0.25 0.004 7.20 7.50 0.272 5.30 5.60 0.197 7.80 8.20 0.291 0. 0.75 0.95 0.021 1. 0. 8º W682510/W682310 D IMENSIONS DTEAIL A b SEATING θ DETAIL A NOM. MAX. - 0.079 - - 0.069 - - 0.015 - 0.010 0.283 0.295 0.209 0.220 0.307 0.323 0.0256 - 0.030 0.037 0.050 - - 0.004 - 8º ...
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... DIMENSION (INCH) MAX. MIN. 2.65 0.093 0.30 0.004 0.51 0.013 0.32 0.009 7.60 0.291 15.60 0.598 1.27 BSC 0.050 BSC 10.65 0.394 0.10 1.27 0.016 8º W682510/W682310 0. PLA N E MAX. 0.104 0.012 0.020 0.013 0.299 0.614 0.419 0.004 0.050 8º Publication Release Date: April 2005 Revision A10 ...
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... ORDERING INFORMATION Product Number Descriptor Key W682510 _ Product Family W682510 Product When ordering W682510 series devices, please refer to the following part numbers. W682310 _ Product Family W682310 Product When ordering W682310 series devices, please refer to the following part numbers. For the latest product information, access Winbond’s worldwide website at HTTP://WWW ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. DESCRIPTION Preliminary Specifications Updates Frequency response updated Add Important Notice Important Notice - 35 - W682510/W682310 Publication Release Date: April 2005 Revision A10 ...