adm6995 ETC-unknow, adm6995 Datasheet
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... ADM6995L 5 port 10/100 Mb/s Single Chip Ethernet Switch Controller ADMtek com.tw . Information in this document is provided in connection with ADMtek products. ADMtek may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. ADMtek ...
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... Interface Description Chapter 3 Function Description Chapter 4. Register Description Chapter 5. Electrical Specification Chapter 6. Packaging Revision History Date 13 Nov 2003 Customer Support ADMtek Incorporated, 2F, No.2, Li-Hsin Rd., Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Sales Information Tel + 886-3-5788879 Fax + 886-3-5788871 Version Change 1.0 1. First release of ADM6995L V1.0 ...
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... Symbol Alignment .................................................................................... 3-3 3.4.6 Symbol Decoding ..................................................................................... 3-3 3.4.7 Valid Data Signal..................................................................................... 3-4 3.4.8 Receive Errors ......................................................................................... 3-4 3.4.9 100Base-X Link Monitor.......................................................................... 3-4 3.4.10 Carrier Sense ........................................................................................... 3-4 3.4.11 Bad SSD Detection................................................................................... 3-5 3.4.12 Far-End Fault .......................................................................................... 3-5 3.5 100Base-TX Transceiver ................................................................................. 3-5 3.5.1 Transmit Drivers...................................................................................... 3-5 3.5.2 Twisted-Pair Receiver.............................................................................. 3-6 3.6 10Base-T Module............................................................................................. 3-6 3.6.1 Operation Modes ..................................................................................... 3-6 3.6.2 Manchester Encoder/Decoder ................................................................. 3-6 3.6.3 Transmit Driver and Receiver ................................................................. 3-7 3.6.4 Smart Squelch .......................................................................................... 3-7 3.7 Carrier Sense.................................................................................................... 3-7 3.8 Jabber Function................................................................................................ 3-7 ADM6995L V1.0 i ...
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... Port0 PVID bit Configuration Register, offset: 0x28h ................. 4-8 4.3.17 Port1 PVID bit Configuration Register, offset: 0x29h ................. 4-8 4.3.18 Port2 PVID bit 11~4 Configuration Register, offset: 0x2ah ................... 4-9 4.3.19 Port3, 4 PVID bit 11~4 Configuration Register, offset: 0x2bh ............... 4-9 4.3.20 VLAN group shift bits Configuration Register, offset: 0x2ch .................. 4-9 4.3.21 Reserved Register, offset: 0x2dh.............................................................. 4-9 ADM6995L V1.0 ii ...
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... Chapter 5 Electrical Specification................................................................................ 5-1 5.1 TX/FX Interface............................................................................................... 5-1 5.1.1 TP Interface ............................................................................................. 5-1 5.1.2 FX Interface ............................................................................................. 5-1 5.2 DC Characteristics ........................................................................................... 5-2 5.2.1 Absolute Maximum Rating....................................................................... 5-2 5.2.2 Recommended Operating Conditions ...................................................... 5-2 5.2.3 DC Electrical Characteristics for 3.3V Operation .................................. 5-2 5.3 AC Characteristics ........................................................................................... 5-3 5.3 AC Characteristics ........................................................................................... 5-3 5.3.1 Power On Reset........................................................................................ 5-3 5.3.2 EEPROM Interface Timing...................................................................... 5-3 5.3.3 GPSI(7-wire) Input Timing ...................................................................... 5-4 5.3.4 GPSI(7-wire) Output Timing ................................................................... 5-4 Chapter 6 Packaging...................................................................................................... 6-1 6.1 128 Pin PQFP Outside Dimension................................................................... 6-1 ADM6995L V1.0 iii ...
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... ADMtek Inc. Figure 1-1 ADM6995L Block Diagram .......................................................................... 1-3 Figure 2-1 5 TP/FX PORT 128 Pin Diagram .................................................................. 2-1 ADM6995L List of Figures V1.0 iv ...
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... Control Pause packet in Full-Duplex mode to prevent packet loss when the buffer is full. When Back Pressure is enabled, and there is no receive buffer available for the incoming packet, the ADM6995L will issue a JAM pattern on the receiving port in Half Duplex mode and transmit the 802.3x Pause packet back to the receiving end in Full Duplex mode ...
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... ADM6995L 1.2 Features • Supports five 10M/100M auto-detect Half/Full duplex switch ports with TX/FX interfaces. • Supports 2048 MAC addresses table. • Supports four queue for QoS • Supports priority features by Port-Based, 802.1p VLAN & IP TOS of packets. • Supports Store & Forward architecture and performs forwarding and filtering at non- blocking full wire speed. • ...
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... PORT2 ... PORTN A/D DIGITAL CONVERTER EQUALIZER DRIVER MLT3 Converter BIAS CLOCK GENERATOR Figure 1-1 ADM6995L Block Diagram Bit Error Rate Canonical Format Indicator Collision Cyclic Redundancy Check Carrier Sense Chip Select Destination Address Data Input Data Output EEPROM Data Input EEPROM Data Output ...
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... ADM6995L EESK ESD FEFI FET FLP GND GPSI IPG LFSR MAC MDIX MII NRZI NRZ PCS PHY PLL PMA PMD QoS QFP RST RXCLK RXD RXDV RXER RXN RXP SA SOHO SSD SQE TOS TP TTL TXCLK TXD TXEN TXN TXP ADMtek Inc. ...
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... ADM6995L 1.5 Conventions 1.5.1 Data Lengths qword dword word byte nibble 1.5.2 Pin Types Pin Type I O I/O OD SCHE PD PU 1.5.2 Register Types Register Type ADMtek Inc. 64-bits 32-bits 16-bits 8 bits 4 bits Description Input Output Bi-directional Open drain Schmitt Trigger internal pull-down internal pull-up Description ...
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... VREF 119 GNDBIAS 120 RTX 121 VCCBIAS 122 VCCA2 123 TXP0 124 TXN0 125 GNDA 126 RXP0 127 RXN0 128 VCCAD ADMtek Inc. ADM6995L Figure 2-1 5 TP/FX PORT 128 Pin Diagram Interface Description 64 GNDIK 63 GFCEN 62 P4FX LDSPD4 57 GNDO 56 VCC3O 55 LDSPD3 ...
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... ADM6995L 2.2 Pin Description by Function ADM6995L pins are categorized into one of the following groups: Section 2.2.1 Twisted Pair Interface Section 2.2.2 Settings Section 2.2.3 LED Interface Section 2.2.4 EEPROM/Management Interface Section 2.2.5 Power/Ground, 48 pins Section 2.2.6 MISC Note: “Section 1.5.2 Pin Types” can be used for reference. 2.2.1 Twisted Pair Interface ...
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... ADM6995L Pin Name 2.2.3 LED Interface Pin Name LNKACT[4:0] 92, 95, 96, 97, 98 DUPCOL[4:3] 103, 106 DUPCOL2 Setting BPEN DUPCOL1 Setting PHYAS1 DUPCOL0 Setting ANEN LDSPD[4:0] 58, 55, 54, 51, 50 ADMtek Inc. Pin# Type If user put 93C66 then data put in Bank0. User can write chip register by 93C66 timing. ...
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... ADM6995L 2.2.4 EEPROM/Management Interface Pin Name EDO EECS EECK Setting XOVEN EDI Setting LEDMODE 2.2.5 Power/Ground, 48 pins Pin Name GNDA 3, 10, 16, 23, 29, 36, 42, 125 VCCA2 6, 7, 19, 20, 32, 33, 45, 122 VCCAD 13, 26, 39, 128 GNDBIAS VCCBIAS GNDPLL VCCPLL GNDIK 47, 52, 64, 76, 93, 83, VCCIK 48, 53, 65, ...
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... ADM6995L 2.2.6 MISC Pin Name CKO25M Control RTX VREF CFG0 TEST 4,5, 14, 15,17, 18, 27,28, NC 61, 59 74, 102, 101, 100, 73, 68, 78, 77, 72, 67, 91, 90, 89 ADMtek Inc. Pin# Type Descriptions 85 O, 25M Clock Output. 8mA 117 O FET Control Signal. The pin is used to control FET for 3.3V to 1.8V regulator. ...
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... IEEE 802.3u auto negotiation 3.3 100Base-X Module The ADM6995L implements 100Base-X compliant PCS and PMA and 100Base-TX compliant TP-PMD as illustrated in Figure 2. Bypass options for each of the major functional blocks within the 100Base-X PCS provides flexibility for various applications. 100Mbits/s PHY loop back is included for diagnostic purpose. ...
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... ADM6995L • A/D Converter • Adaptive Equalizer and timing recovery module • NRZI/NRZ and serial/parallel decoder • De-scrambler • Symbol alignment block • Symbol Decoder • Collision Detect Block • Carrier sense Block • Stream decoder block RXD[1:0] RXD[3:0] BP_ALIGN CRSDV TXEN TXD[1:0] 3 ...
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... Symbol Alignment The symbol alignment circuit in the ADM6995L determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the de- scrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. ...
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... Without reliable data reception, the link monitor will halt both transmit and receive operations until such time that a valid link is detected. The ADM6995L performs the link integrity test as outlined in IEEE 100Base-X (Clause 24) link monitor state diagram. The link status is multiplexed with 10Mbits/s link status to form the reportable link status bit in serial management register 1h, and driven to the LNKACT pin ...
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... If this condition is detected, then the ADM6995L will assert RXER and present RXD[3:0] = 1110 to the internal MII for the cycles hat correspond to received 5B code- groups until at least two idle code-groups are detected. Once at least two idle code groups are detected, RXER and CRS become de-asserted ...
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... Polarity detection and correction 3.6.1 Operation Modes The ADM6995L 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In half-duplex mode, the ADM6995L functions as an IEEE 802.3 compliant transceiver with fully integrated filtering. The COL signal is asserted during collisions or jabber events, and the CRS signal is asserted during transmit and receive. In full duplex mode the ADM6995L can simultaneously transmit and receive data ...
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... For 10 Mbits/s full duplex and repeater mode operations, the CRS is asserted only due to receive activity. 3.8 Jabber Function The jabber function monitors the ADM6995L output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than ADMtek Inc. Function Description ...
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... For further detail regarding auto negotiation, refer to Clause 28 of the IEEE 802.3u specification. The ADM6995L supports four different Ethernet protocols, so the inclusion of auto negotiation ensures that the highest performance protocol will be selected based on the ability of the link partner ...
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... ADM6995L 3.13 Memory Block ADM6995L build in memory is divided as two blocks. One is MAC addressing table and another one is data buffer. MAC address Learning Table size is 2048 entry with each entry occupy eight bytes length. These eight bytes data include 6 bytes source address, VLAN information, Port information and Aging counter ...
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... ADM6995L 3.15.1 Address Learning The ADM6995L uses a hash algorithm to learn the MAC address and can learn MAC addresses. Address is stored in the Address Table. The ADM6995L searches for the Source Address (SA incoming packet in the Address Table and acts as below: If the SA was not found in the Address Table (a new address), the ADM6995L waits until the end of the packet (non-error packet) and updates the Address Table ...
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... CRC. Dribbling packing with good CRC value will accept by ADM6995L. In case of bypass mode enabled, ADM6995L will support tag and untagged packets with size up to 1522 bytes. In case of non-bypass mode, ADM6995L will support tag packets up to 1526bytes, untagged packets up to 1522bytes ...
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... PVID value ( user define 4bits to map 16 groups written at register 13 to register the configuration content of each port. ADM6995L also supports 16 802.1Q VLAN groups. In VLAN four bytes tag include twelve VLAN ID. ADM6995L learn user define four bits of VID. If user need to use this ADMtek Inc. Per Port Falling Threshold ...
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... N:1 rate. See EEPROM Reg.0x10h. This priority function can set three ways as below Port Base: Set specific port at specific queue. ADM6995L only check the port priority and not check packet’s content VLAN and TOS. ADMtek Inc. ...
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... ADM6995L * By VLAN first: ADM6995L check VLAN three priority bit first then IP TOS priority bits TOS first: ADM6995L check IP TOS three priority bit first then VLAN three priority bits. If port set at VLAN/TOS priority but receiving packet without VLAN or TOS information then port base priority will be used . ...
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... ADM6995L Chapter 4 Register Description 4.1 EEPROM Content EEPROM provides ADM6995L many options setting such as: • Port Configuration: Speed, Duplex, Flow Control Capability and Tag/ Untag. • VLAN & TOS Priority Mapping • Broadcast Storming rate and Trunk. • Fiber Select, Auto MDIX select • ...
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... RO The value must be 4154h(AT) Note: ADM6995L will check register 0 value before read all EEPROM content. If this value does not match with 0x4154h then he other values in EEPROM will be useless. ADM6995L will use internal default value. User cannot write Signature register when programming ADM6995L internal register. ...
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... R/W Enable port-base priority. 1: Port Base Priority. 0: VLAN or TOS. If packet without VLAN or TOS then port priority turn on. Note: If this bit turn on then ADM6995L will not check TOS or VLAN as priority reference. ADM6995L will check port base priority only. ADM6995L default is bypass mode which checks port base priority only. ...
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... Type Description 5:0 RO Reserved 6 R/W Enable IPG leveling. 1/92 bit. 0/96 bit. Note: When this bit is enabled ADM6995L will transmit packet out at 92 bit IPG to clean buffer. If user disables this function then ADM6995L will transmit packet at 96 bit. 7 R/W Enable Trunk. 1: enable Port3 Trunk port. 0: disable. 14:8 ...
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... Ethernet Packet from Layer 2 Preamble/SFD Destination (6 bytes) Byte 0~5 4.3.9 VLAN Packet ADM6995L will check packet byte 12 &13. If byte[12:13]=8100h then this packet is a VLAN packet Tag Protocol TD 8100 Byte 12~13 Byte 14~15: Tag Control Information TCI Bit[15:13]: User Priority 7~0 Bit 12: Canonical Format Indicator (CFI) Bit[11~0]: VLAN ID ...
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... ADM6995L 4.3.10 TOS IP Packet ADM6995L check byte 12 &13 if this value is 0800h then ADM6995L knows this is a TOP priority packet. Type 0800 Byte 12~13 IP header define Byte 14 Bit[7:0]: IP protocol version number & header length. Byte 15: Service type Bit[7~5]: IP Priority (Precedence ) from 7~0 Bit 4: No Delay (D) ...
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... ADM6995L Note (Continued): - per port rising threshold 00 All Disable 100TX Not All Disable 100TX - per port falling threshold 00 All Disable 100TX Not All Disable 100TX Bit 2: Broadcast Storming Enable. 0/Disable. 1/Enable. Bit 4: CRC check disable. 1/ Disable. 0/Enable. Bit 7: Aging Disable. 1/Disable. 0/Enable. ...
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... ADM6995L Bits Type Description 11 R/W Reserved 13:12 R/W Reserved 14 R/W Reserved 15 R/W Drop packet when excessive collision happen enable. 1: enable, 0: disable. 4.3.14 VLAN mapping table registers, offset: 0x22h ~ 0x13h Bits Type Description 8:0 R/W VLAN mapping table. 15:9 RO Reserved Note: 16 VLAN Group: See Register 0x2ch bit 11=0 Bit0: Port0 Bit6: Port3 Select the VLAN group ports is to set the corresponding bits to 1 ...
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... R/W Control reserved MAC (0180C2000001) 1: Forward, 0: Discard. 15 R/W Control reserved MAC (0180C2000000) 1: Forward, 0: Discard. Note: Bit[10:8]: VLAN Tag shift register. ADM6995L will select 4 bit from total 12 bit VID as VLAN group reference. Bit[15:12]: IEEE 802.3 reserved DA forward or drop police. 4.3.21 Reserved Register, offset: 0x2dh Bits ...
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... ADM6995L 4.3.22 Reserved Register, offset: 0x2eh Bits Type Description 15:0 R/W Reserved 4.3.23 PHY Restart, offset: 0x2fh Bits Type Description 15:0 R/W Write 0x0000h to this register will restart internal PHYs. 4.3.24 Miscellaneous Configuration Register, offset: 0x30h Bits Type Description 0 R/W Reserved 1 R/W Reserved 2 R/W Reserved 4:3 R/W Reserved 5 R/W MAC Clone Enable Bit[1]. 6 R/W Reserved ...
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... ADM6995L Bits Type Description 0 = The switch will add length to the P2 counter. 14:12 R/W Port 3 Meter Threshold Control. Reference table below. 15 R/W Receive Packet Length Counted on the Source Port The switch will add length to the P3 counter. Note: Reference Table 000 001 256K 512K 4.3.26 Bandwidth Control Register 4~5, offset: 0x32h ...
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... Reset signal is control by CPU with at least 100ms low. Point1 is Reset rising edge. CPU must prepare proper value on EECS(0), EESK, EDI, EDO(1) before this rising edge. ADM6995L will read this value into chip at Point2. CPU must keep these values over point2. Point2 is 200ns after Reset rising edge. ...
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... CS go down after write a command, SK must issue at least one clock. This is a difference between ADM6995L with EEPROM write timing. If system without EEPROM then user must write ADM6995L internal register by 93C66 timing. If user uses EEPROM then the writing timing is depend on EEPROM type. ...
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... ADM6995L Register 0x0bh 0x0ch 0x0dh 0x0eh 0x0fh 0x10h 0x11h 0x12h 0x13h 0x14h 0x15h 0x16h 0x17h 0x18h 0x19h 0x1ah 0x1bh 0x1ch 0x1dh 0x1eh 0x1fh 0x20h 0x21h 0x22h 0x23h 0x24h 0x25h 0x26h 0x27h 0x28h 0x29h 0x2ah 0x2bh 0x2ch 0x2dh 0x2eh 0x2fh 0x30h 0x31h ...
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... ADM6995L Register 0x37h 0x38h 0x39h 0x3ah 0x3bh 0x3ch 4.6 Serial Register Description 4.6.1 Chip Identifier Register, offset: 0x00h Bits Type Description 3:0 RO 0000 (Version number) 31:4 RO 0x0007101h 4.6.2 Port Status 0 Register, offset: 0x01h Bits Type Description 0 RO Port 0 Linkup Status: 1: Link is established. 0: Link is not established Port 0 Speed Status: ...
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... ADM6995L Bits Type Description 1: 802.3X on for full duplex or back pressure on for half duplex. 0: Flow Control Disable 12 RO Reserved 13 RO Reserved 14 RO Reserved 15 RO Reserved 16 RO Port 2 Linkup Status: 1: Link is established. 0: Link is not established Port 2 Speed Status: 1: 100Mb Mb Port 2 Duplex Status 1: Full Duplex ...
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... ADM6995L Bits Type Description 0: Flow Control Disable 4.6.3 Port Status 1 Register, offset: 0x02h Bits Type Description 0 RO Reserved 2:1 RO Reserved 3 RO Reserved 4 RO Reserved 31:5 RO Reserved 4.6.4 Cable Broken Status Register, offset: 0x03h Bits Type Description 1:0 RO Port 0 Cable Broken Length 2 RO Port 0 Cable Broken 4:3 RO Reserved ...
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... ADM6995L Bits Type Description 6 RO Overflow of Port 3 Receive Packet Count 7 RO Overflow of Port 4 Receive Packet Count 8 RO Reserved 9 RO Overflow of Port 0 Receive Packet Byte Count 10 RO Reserved 11 RO Overflow of Port 1 Receive Packet Byte Count 12 RO Reserved 13 RO Overflow of Port 2 Receive Packet Byte Count ...
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... ADM6995L Bits Type Description 3 RO Reserved 4 RO Overflow of Port 2 Collision Count 5 RO Reserved 6 RO Overflow of Port 3 Collision Count 7 RO Overflow of Port 4 Collision Count 8 RO Reserved 9 RO Overflow of Port 0 Error Count 10 RO Reserved 11 RO Overflow of Port 1 Error Count 12 RO Reserved 13 RO Overflow of Port 2 Error Count ...
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... Register +1, Register ( Register is even number). Register, Register-1(Register is Odd number). Example: Read Register 00h then ADM6995L will drive 0x01h & 0x00h. Read Register 03h then ADM6995L will drive 0x03h & 0x02h. Idle: EESK must send at least one clock at idle time. ...
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... ADM6995L Preamble: At least 32 continuous “1”. Start: 01(2 bits) Opcode bits, Reset command) Device Address: Chip physical address as PHYAS[1:0]. Reset_type: Reset counter by port number or by counter index. 1: Clear dedicate port’s all counters. 0: Clear dedicate counter. Port_number or counter index: User define clear port or counter. ...
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... ADM6995L Chapter 5 Electrical Specification 5.1 TX/FX Interface 5.1.1 TP Interface Transformer requirement: . TX/RX rate 1:1 . TX/RX central tap connect together to VCCA2. User can change TX/RX pin for easy layout but do not change polarity. ADM6995L supports auto polarity on receiving side. 5.1.2 FX Interface ADMtek Inc. Electrical Specification 5-1 ...
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... ADM6995L 5.2 DC Characteristics 5.2.1 Absolute Maximum Rating Symbol Parameter V Power Supply CC Vcca2 TX line driver Vccpll PLL voltage Vccik Digital core voltage V Input Voltage IN Vout Output Voltage TSTG Storage Temperature PD Power Dissipation ESD ESD Rating 5.2.2 Recommended Operating Conditions Symbol Parameter Vcc Power Supply Vcca2 ...
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... ADM6995L 5.3 AC Characteristics 5.3 AC Characteristics 5.3.1 Power On Reset RST* All Configuration Pins Symbol Parameter TRST RST Low Period TCONF Start of Idle Pulse Width 5.3.2 EEPROM Interface Timing 0us EECS EESK tEWDD EEDO EEDI Symbol Parameter TESK EESK Period TESKL EESK Low Period TESKH EESK High Period ...
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... ADM6995L 5.3.3 GPSI(7-wire) Input Timing 0ns GPSI_TXCLK GPSI_TXD GPSI_TXEN Symbol Parameter TCK GPSI_TXCLK Period TCKL GPSI_TXCLK Low Period TCKH GPSI_TXCLK High Period TTXS GPSI_TXD, GPSI_TXEN to GPSI_TXCLK Rising Setup Time TTXH GPSI_TXD, GPSI_TXEN to GPSI_TXCLK Rising Hold Time 5.3.4 GPSI(7-wire) Output Timing 0ns ...
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... ADM6995L Symbol Parameter Output Delay ADMtek Inc. Conditions Min Typical Electrical Specification Max Units 5-5 ...
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... ADM6995L Chapter 6 Packaging 6.1 128 Pin PQFP Outside Dimension ADMtek Inc. 17.2 +/- 0.2 mm 14.0 +/- 0.1 mm 12.5 mm 0.5 mm Appendix 6-1 ...