lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 176

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
BITS
19
18
17
16
15
14
13
12
10
11
9
8
7
6
GP Timer (GPT_INT)
This interrupt is issued when the
(GPT_CNT)
RESERVED
Power Management Interrupt Event (PME_INT)
This interrupt is issued when a Power Management Event is detected as
configured in the
interrupt functions independent of the PME signal, and will still function if
the PME signal is disabled. Writing a '1' clears this bit regardless of the
state of the PME hardware signal. In order to clear this bit, all unmasked
bits in the
cleared.
Note:
TX Status FIFO Overflow (TXSO)
This interrupt is generated when the TX Status FIFO overflows.
Receive Watchdog Time-out (RWT)
This interrupt is generated when a packet larger than 2048 bytes has been
received by the Host MAC.
Note:
Receiver Error (RXE)
Indicates that the Host MAC receiver has encountered an error. Please
refer to
the conditions that will cause an RXE.
Transmitter Error (TXE)
When generated, indicates that the Host MAC transmitter has encountered
an error. Please refer to
for a description of the conditions that will cause a TXE.
GPIO Interrupt Event (GPIO)
This bit indicates an interrupt event from the General Purpose I/O. The
source of the interrupt can be determined by polling the
I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
TX Data FIFO Underrun Interrupt (TDFU)
This interrupt is generated when the TX Data FIFO underruns.
TX Data FIFO Overrun Interrupt (TDFO)
This interrupt is generated when the TX Data FIFO is full, and another write
is attempted.
TX Data FIFO Available Interrupt (TDFA)
This interrupt is generated when the TX Data FIFO available space is
greater than the programmed level in the
the
TX Status FIFO Full Interrupt (TSFF)
This interrupt is generated when the TX Status FIFO is full.
TX Status FIFO Level Interrupt (TSFL)
This interrupt is generated when the TX Status FIFO reaches the
programmed level in the
Register
RX Dropped Frame Interrupt (RXDF_INT)
This interrupt is issued whenever a receive frame is dropped by the Host
MAC.
FIFO Level Interrupt Register
Section 9.9.5, "Receiver Errors," on page 137
The Interrupt De-assertion interval does not apply to the PME
interrupt.
This can occur when the switch engine adds a tag to a non-tagged
jumbo packet that is originally larger than 2044 bytes.
(FIFO_INT).
Power Management Control Register (PMT_CTRL)
wraps past zero to FFFFh.
Power Management Control Register
Section 9.8.8, "Transmitter Errors," on page 132
TX Status Level
DESCRIPTION
General Purpose Timer Count Register
(FIFO_INT).
DATASHEET
TX Data Available Level
field of the
176
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
FIFO Level Interrupt
for a description of
(PMT_CTRL). This
General Purpose
must first be
field of
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
TYPE
RO
RO
SMSC LAN9311/LAN9311i
DEFAULT
Datasheet
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
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