lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 91

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
Auto-negotiation is started by the occurrence of any of the following events:
Note: Refer to
On detection of one of these events, the PHY begins auto-negotiation by transmitting bursts of Fast
Link Pulses (FLP). These are bursts of link pulses from the 10M TX Driver. They are shaped as Normal
Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists
of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP burst. The
16 even-numbered pulses, which may be present or absent, contain the data word being transmitted.
Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE
802.3 clause 28. In summary, the PHY advertises 802.3 compliance in its selector field (the first 5 bits
of the Link Code Word). It advertises its technology ability according to the bits set in the
Auto-Negotiation Advertisement Register
There are 4 possible matches of the technology abilities. In the order of priority these are:
If the full capabilities of the PHY are advertised (100M, full-duplex), and if the link partner is capable
of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If the link
partner is capable of half and full-duplex modes, then auto-negotiation selects full-duplex as the highest
performance mode.
Once a speed and duplex match has been determined, the link code words are repeated with the
acknowledge bit set. Any difference in the main content of the link code words at this time will cause
auto-negotiation to re-start. Auto-negotiation will also re-start if all of the required FLP bursts are not
received.
Writing the
software control of the capabilities advertised by the PHY. Writing the
Advertisement Register (PHY_AN_ADV_x)
x PHY Basic Control Register
will be advertised. Auto-negotiation can also be disabled via software by clearing bit 12 of the
PHY Basic Control Register
10M PLL (analog)
10M TX Driver (analog)
Power-On Reset (POR)
Hardware reset (nRST)
PHY Software reset (via
Control Register
PHY Power-down reset
PHY Link status down (bit 2 of the
cleared)
Setting the
restart)
Digital Reset (via bit 0 of the
Issuing an EEPROM Loader RELOAD command
100M Full Duplex (highest priority)
100M Half Duplex
10M Full Duplex
10M Half Duplex (lowest priority)
Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
Port x PHY Basic Control Register
Section 4.2, "Resets," on page 36
(PHY_BASIC_CONTROL_x))
(Section 7.2.9, "PHY Power-Down Modes," on page
Reset Control Register
(PHY_BASIC_CONTROL_x).
(PHY_BASIC_CONTROL_x), bit 9 must be set before the new abilities
Reset Control Register
DATASHEET
Port x PHY Basic Status Register (PHY_BASIC_STATUS_x)
(PHY_AN_ADV_x).
91
does not automatically re-start auto-negotiation. The
(PHY_BASIC_CONTROL_x), bit 9 high (auto-neg
for information on these and other system resets.
(RESET_CTL), or bit 15 of the
(Section 10.2.4, "EEPROM Loader," on page
(RESET_CTL))
Port x PHY Auto-Negotiation
94)
Revision 1.2 (04-08-08)
Port x PHY Basic
bits [8:5] allows
Port x PHY
Port x
150)
Port
is