lan9303m Standard Microsystems Corp., lan9303m Datasheet - Page 27

• Manufacturer Part Number: lan9303m
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Dual Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
PINS
NUM
1
1
1
Port 1 MII Input
Port 1 MII Input
Port 1 MII Input
Data Valid
Reference
NAME
Clock
Error
P1_INCLK
SYMBOL
P1_INDV
P1_INER
Table 3.4 Port 1 MII/RMII Pins (continued)
DATASHEET
BUFFER
O12/O16
TYPE
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
IS
IS
IS
IS
IS
IS
-
-
27
MII MAC Mode: This pin is the RX_DV signal from
the external PHY and indicates valid data on
P1_IND[3:0] and P1_INER.
MII PHY Mode: This pin is the TX_EN signal from
the external MAC and indicates valid data on
P1_IND[3:0] and P1_INER. The pull-down and
input buffer are disabled when the
in the
(P1_MII_BASIC_CONTROL).
RMII PHY Mode: This pin is the TX_EN signal from
the external MAC and indicates valid data on
P1_IND[1:0]. The pull-down and input buffer are
disabled when the
Basic Control Register
(P1_MII_BASIC_CONTROL).
Internal PHY Mode: This pin is not used.
MII MAC Mode: This pin is the RX_ER signal from
the external PHY and indicates a receive error in
the packet.
MII PHY Mode: This pin is the TX_ER signal from
the external MAC and indicates that the current
packet should be aborted. The pull-down and input
buffer are disabled when the
Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL).
RMII PHY Mode: This pin is not used.
Internal PHY Mode: This pin is not used.
MII MAC Mode: This pin is an input and is used as
the reference clock for the P1_IND[3:0], P1_INER,
and P1_INDV pins. It is connected to the receive
clock of the external PHY.
MII PHY Mode: This pin is an output and is used
as the reference clock for the P1_IND[3:0],
P1_INER, and P1_INDV pins. It is connected to the
transmit clock of the external MAC. The output
driver is disabled when the
Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL). When operating at
200MBps, the choice of drive strength is based on
the setting of the
in the
(P1_MII_BASIC_CONTROL). A low selects a 12
mA drive, while a high selects a 16 mA drive. A
series terminating resistor is recommended for the
best PCB signal integrity.
RMII PHY Mode: This pin is not used.
Internal PHY Mode: This pin is not used.
Port 1 MII Basic Control Register
Port 1 MII Basic Control Register
RMII/Turbo MII Clock Strength
DESCRIPTION
Isolate
bit is set in the
Isolate
Isolate
Revision 1.3 (08-27-09)
Isolate
bit is set in the
bit is set in the
Port 1 MII
bit is set
bit