lan9303m Standard Microsystems Corp., lan9303m Datasheet - Page 30

• Manufacturer Part Number: lan9303m
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Dual Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Revision 1.3 (08-27-09)
PINS
NUM
1
1
Reference
Port 1 MII
Port 1 MII
Collision
NAME
Output
Clock
P1_OUTCLK
SYMBOL
P1_COL
Table 3.4 Port 1 MII/RMII Pins (continued)
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
DATASHEET
BUFFER
O12/O16
IS/O12/
TYPE
(PD)
(PD)
(PD)
(PU)
(PU)
O16
O8
IS
IS
-
30
MII MAC Mode: This pin is an input and is used as
the reference clock for the P1_OUTD[3:0] and
P1_OUTDV pins. It is connected to the transmit
clock of the external PHY.
MII PHY Mode: This pin is an output and is used
as the reference clock for the P1_OUT[3:0] and
P1_OUTDV pins. It is connected to the receive
clock of the external MAC. The output driver is
disabled when the
Basic Control Register
(P1_MII_BASIC_CONTROL). When operating at
200MBps, the choice of drive strength is based on
the setting of the
in the
(P1_MII_BASIC_CONTROL). A low selects a 12
mA drive, while a high selects a 16 mA drive. A
series terminating resistor is recommended for the
best PCB signal integrity.
RMII PHY Mode: This pin is an input or an output
running at 50 MHz and is used as the reference
clock for the P1_IND[1:0], P1_INDV,
P1_OUTD[1:0], and P1_OUTDV pins. The choice
of input verses output is based on the setting of the
RMII Clock Direction
Control Register
low selects P1_OUTCLK as an input and a high
selects P1_OUTCLK as an output.
As an input, the pull-down is normally enabled. The
input buffer and pull-down are disabled when the
Isolate
Register
As an output, the input buffer and pull-down are
disabled. The choice of drive strength is based on
the setting of the
in the
(P1_MII_BASIC_CONTROL). A low selects a 12
mA drive, while a high selects a 16 mA drive. The
output driver is disabled when the
in the
(P1_MII_BASIC_CONTROL). A series terminating
resistor is recommended for the best PCB signal
integrity.
Internal PHY Mode: This pin is not used.
MII MAC Mode: This pin is an input from the
external PHY and indicates a collision event.
MII PHY Mode: This pin is an output to the external
MAC indicating a collision event. The output driver
is disabled when the
MII Basic Control Register
(P1_MII_BASIC_CONTROL).
RMII PHY Mode: This pin is not used.
Internal PHY Mode: This pin is not used.
Port 1 MII Basic Control Register
Port 1 MII Basic Control Register
Port 1 MII Basic Control Register
bit is set in the
(P1_MII_BASIC_CONTROL).
(P1_MII_BASIC_CONTROL). A
RMII/Turbo MII Clock Strength
RMII/Turbo MII Clock Strength
DESCRIPTION
Isolate
Isolate
bit in the
Port 1 MII Basic Control
SMSC LAN9303M/LAN9303Mi
bit is set in the
bit is set in the
Port 1 MII Basic
Isolate
Port 1 MII
bit is set
Datasheet
Port 1
bit
bit