mc44827 Freescale Semiconductor, Inc, mc44827 Datasheet - Page 6

• Manufacturer Part Number: mc44827
• Description: Low-power Tuning Circuit
• Manufacturer: Freescale Semiconductor, Inc

Definition of Permissible Bus Protocols
1. Bus Protocol for 18 Bit
2. Bus Protocol for 19 Bit
3. Bus Protocol for Test and Further Features (34 Bit)
Definition of the Bits for Test and Features
Bit T0: Defines the Charge Pump Current of the
Bit T 0 :
Bits T1 and T2: Define the Digital Function of the Phase
Bits T 1 and T 2 :
Bit T4: Switches the Internal Frequencies F ref and
Bit T 4 :
NOTE: 1. The phase comparator pulls high if the input frequency is too
NOTE: Bits B2 and B3 have to be one in this case.
T2
0
0
1
1
6
T0 = 0
T 0
T4 = 0
T 4
B3 B2 B1 B0 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3
N2 N1 N0
Max Counting Ratio 16363
N14 is Reset Internally
B3 B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4
N3 N2 N1 N0
Max Counting Ratio 32767
N14 = MSB; N 0 = LSB
Minimum Counting Ratio Always 17
B3 = First Shifted Bit
N0 = Last Shifted Bit
B3 B2 B1 B0 N14 N0 Y6 T5 T4 Y3 T2 T1 T0 X7
X6 X1 X0
– X0 to X7: Are Random
– Y3 and Y6: Are Not Used
B3 = First Shifted Bit
X0 = Last Shifted Bit
= 1
= 1
B0 to B3: Control of Band Buffers
N0 to N14: Programmable Divider Counting Ratio
T0 to T2: Control the Phase Comparator (Note 1)
T4: Switches Test Signals to the Buffer Outputs
T5: Division Ratio of the Reference Divider
T1
0
1
0
1
Phase Comparator
FBY2 to the Buffer Outputs (B2, B3)
F ref is the reference frequency.
FBY2 is the output frequency of the programmable divider,
divided by two.
B Version T5 = “X”
high and it pulls low when the input frequency is too low.
(Inversion by Operational Amplifier) The phase comparator
generates a fixed duration offset pulse for each comparison
pulse. This guarantees operation in the linear region.
The offset pulse is a positive current pulse (upper source).
State
Pump Current 50 A Typical
Pump Current 15 A Typical
Normal Operation
F ref Switched to Buffer Output B2
FBY2 Switched to Buffer Output B3
1
2
3
4
Comparator
Normal Operation
High Impedance (3–State)
Upper Source “On”, Lower Source “Off”
Lower Source “On”, Upper Source “Off”
Output Function of Phase Comparator
MC44827/27B
Bit T5: Defines the Division Ratio of the Reference
Bit T 5 :
OPERATING DESCRIPTION
Introduction
application are shown in Figures 1 and 8. A discussion of the
features and function of each of the internal blocks is given.
The Programmable Divider
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
N = 16384 x N14 + 8132 x N13 +
programmable divider is set to a counting ratio of N = 256 or
higher.
The Prescaler
guarantees high input sensitivity.
The Phase Comparator
sensitive and has very low output leakage current in the high
impedance state.
Lock Detector
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.
20
NOTES:
Protection
NOTE: The division ratio of the reference divider can only be
T5 = 0
T 5
A representative block diagram and typical system
The programmable divider is a presettable down counter.
Since latches A receive the data asynchronously with the
The division ratio definition is given by:
Maximum Ratio 32767
(16363 in case of 18 bit bus protocol)
Minimum Ratio 17
N0
At power–on the whole bus receiver is reset and the
The divide by 8 prescaler has a preamplifier which
The phase comparator is both phase and frequency
The lock–detector output is low in lock. The output goes
25 V
= 1
Figure 6. Equivalent Circuit of the Integrated
programmed in the 34 bit bus protocol.
In the standard bus protocol the division ratio is 512.
(The power–up reset POR sets the division ratio to 512).
On “B–version”, T5 = “X”. Division ratio 1024 is fixed.
Divider
I B + I SUB = 5.5 mA Typical
I B = Base Current
I SUB = Substrate Current of PNP
Gnd
N14 are the different bits for frequency information.
“On”/“Off”
Division Ratio 512
Division Ratio 1024
I B
MOTOROLA ANALOG IC DEVICE DATA
Band Buffers
I SUB
+ 4 x N2 + 2 x N1 + N0
B0 B3
Out
Saturation Voltage
0.15 V Typical
0.3 V Max
V CC3 12 V
30 mA (40 mA
at 0 to 80 C)