at42qt2160 ATMEL Corporation, at42qt2160 Datasheet - Page 18

• Manufacturer Part Number: at42qt2160
• Description: Qslide?, 16-key Qmatrix? Sensor Ic
• Manufacturer: ATMEL Corporation

5.3
5.4
18
START and STOP Conditions
Address Packet Format
AT42QT2160
Figure 5-2.
The host initiates and terminates a data transmission. The transmission is initiated when the
host issues a START condition on the bus, and is terminated when the host issues a STOP
condition. Between START and STOP conditions, the bus is considered busy. As shown below,
START and STOP conditions are signaled by changing the level of the SDA line when the SCL
line is high.
Figure 5-3.
All address packets are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit
and an acknowledge bit. If the READ/WRITE bit is set, a read operation is performed, otherwise
a write operation is performed. When the device recognizes that it is being addressed, it will
acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An address packet consisting of
a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively.
The most significant bit of the address byte is transmitted first. The address sent by the host
must be consistent with that selected with the option jumpers.
Data Transfer
START and STOP Conditions
SDA
SCL
SDA
SCL
START
Data Stable
Data Change
Data Stable
STOP
9502A–AT42–07/08