at42qt2160 ATMEL Corporation, at42qt2160 Datasheet - Page 22

• Manufacturer Part Number: at42qt2160
• Description: Qslide?, 16-key Qmatrix? Sensor Ic
• Manufacturer: ATMEL Corporation

6.3.2
6.4
6.5
22
SDA, SCL
CHANGE Pin
AT42QT2160
Reading Data From the Device
If the host sends more than one data byte, they will be written to consecutive memory
addresses. The device automatically increments the target memory address after writing each
data byte. After writing the last data byte, the host should send the STOP condition.
The host should not try to write beyond address 255 because the device will not increment the
internal memory address beyond this.
The sequence of events required to read data from the device is shown next.
The host initiates the transfer by sending the START condition, and follows this by sending the
slave address of the device together with the Write-bit. The device sends an ACK. The host then
sends the memory address within the device it wishes to read from. The device sends an ACK.
The host must then send a STOP and a START condition followed by the slave address again
but this time accompanied by the Read-bit. The device will return an ACK, followed by a data
byte. The host must return either an ACK or NACK. If the host returns an ACK, the device will
subsequently transmit the data byte from the next address. Each time a data byte is transmitted,
the device automatically increments the internal address. The device will continue to return data
bytes until the host responds with a NACK. The host should terminate the transfer by issuing the
STOP condition.
The
I
termination resistors (Rp) pull the line up to Vdd if no
The termination resistors commonly range from 1
rise times on SDA and SCL meet the
The CHANGE pin is an active low open drain output that can be used to alert the host of any
changes to any of the 5 status bytes (address 2 to 6), thus reducing the need for wasteful
I
communicate with the device, except when the CHANGE pin goes active.
CHANGE goes inactive again only when the host performs a read from all status bytes which
have changed.
Poll rate: The host can make use of the CHANGE pin output to initiate a communication; this will
guarantee the optimal polling rate.
If the host cannot make use of the CHANGE pin, the poll rate should be no faster than once per
matrix scan (see
will slow down the chip operation.
The CHANGE pin requires a pull-up resistor, with a typical value of ~100kΩ.
2
2
C
C
-compatible master and slave devices can only drive these lines low or leave them open. The
-compatible communications. After setting up the QT2160, the host can simply not
I
2
C
-compatible bus transmits data and clock with SDA and SCL. They are open-drain; that is
S
Section 10.4 on page
SLA+W
Data 1
A
A
Host to Device
MemAddress
Data 2
I
2
C
44). Anything faster will not provide new information and
-compatible specifications (1
A
A
kΩ
P
I
to 10
2
S
C
-compatible device is pulling it down.
Device to Host
kΩ
SLA+R
and should be chosen so that the
Data n
µ
s maximum).
A
/A
P
9502A–AT42–07/08