at42qt2160 ATMEL Corporation, at42qt2160 Datasheet - Page 19

• Manufacturer Part Number: at42qt2160
• Description: Qslide?, 16-key Qmatrix? Sensor Ic
• Manufacturer: ATMEL Corporation

5.5
5.6
9502A–AT42–07/08
Data Packet Format
Combining Address and Data Packets Into a Transmission
Figure 5-4.
All data packets are 9 bits long, consisting of one data byte and an acknowledge bit. During a
data transfer, the host generates the clock and the START and STOP conditions, while the
Receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by
the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA
line high, a NACK is signaled.
A transmission consists of a START condition, an SLA+R/W, one or more data packets and a
STOP condition. The wired-ANDing of the SCL line is used to implement handshaking between
the host and the device. The device extends the SCL low period by pulling the SCL line low
whenever it needs extra time for processing between the data transmissions.
Holding down either SCL or SDA for clock stretching or any other purpose will slow down the
operation of the QT2160. If SCL or SDA is continuously held low for more than ~12ms, this will
be deemed as a error condition and the
Note: Each write or read cycle must end with a STOP condition. The QT2160 may not respond
correctly if a cycle is terminated by a new START condition.
SDA
SCL
Address Packet Format
START
Addr MSB
1
I
2
C
2
-compatible unit reset.
Addr LSB R/W
7
8
AT42QT2160
ACK
9
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