lm4312 National Semiconductor Corporation, lm4312 Datasheet
lm4312
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lm4312 Summary of contents
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... Interface Serializer with Optional Dithering and Look Up Table General Description The LM4312 is a MPL-2 Serializer (SER) that accepts a 24- or 18-RGB interface and serializes this wide bus to 3 differ- ential signals. The optional Dithering feature can reduce 24- bit RGB to 18-bit RGB. The optional Look Up Table (Three X 256 X 8 bit RAM) is provided for independent color correction. 18-bit Bufferless displays from QVGA (320 x 240 > ...
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Pin Descriptions No. Pin Name of Pins MPL-2 SERIAL BUS PINS DD0P, DD0M, 4 DD1P, DD1M DCP, DCM 2 SPI INTERFACE and CONFIGURATION PINS SPI_CSX 1 SPI_SCL 1 SPI_DI 1 SPI_DO 1 PD* 1 RES1 VIDEO INTERFACE ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS Input/Output Voltage MPL-2 Output Voltage Junction Temperature Storage Temperature ESD Ratings: HBM, 1.5 ...
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Symbol Parameter SUPPLY CURRENT I Total Supply Current - DD RGB24 Mode. (Note 4) Total Supply Current - RGB18 Mode. I Supply Current—Disable DDZ Power Down Modes PD Power Dissipation Switching Characteristics Over recommended operating supply and temperature ranges unless ...
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Recommended Input Timing Requirements (PCLK and SPI) Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter PIXEL CLOCK (PCLK) f Pixel Clock Frequency PCLK PCLK Pixel Clock Duty Cycle DC t Input Transition Time T ...
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Timing Diagrams www.national.com FIGURE 1. Input Timing for RGB Interface FIGURE 2. Serial Data Valid FIGURE 3. Stop Pixel Clock (PCLK) Power Down FIGURE 4. Stop Pixel Clock (PCLK) Power Up 6 30011626 30011616 30011629 30011630 ...
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... Functional Description The LM4312 is a Mobile Pixel Link two Serializer that serial- izes a 24-bit RGB plus three control signals (VS, HS, and DE) to two MPL-2 DD lines plus the serial clock DC line. 18-bit RGB, 24-bit RGB, or optionally 24-bit RGB data is dithered to 18 bits and then serialized and level translated to MPL-2 by the SER ...
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... BUS OVERVIEW The LM4312 is a multi-lane MPL-2 Serializer that supports an 18-bit or 24-bit RGB source interface. The MPL-2 physical layer is purpose-built for robustness, low power and low EMI data transmission while requiring the fewest number of signal lines. No external line components are required, as termina- tion is provided internal to the MPL-2 receiver ...
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... RGB VIDEO INTERFACE The LM4312 is transparent to data format and control signal polarity timing. Each PCLK, RGB inputs, HS, VS and DE are sampled on the rising edge of the PCLK. A PCLK by PCLK representation of these signals is duplicated on the opposite device after being transferred across the MPL-2 interface. ...
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... The look up table is comprised of three 256 Byte SRAMs. It may be used for independent color correction. When the LM4312 is in the 24-bit RGB mode, the full 8-bits per color are used for addressing the 256 Bytes for each color. When the LM4312 is used in an 18-bit RGB mode and the LUT is de- sired, all 8-bits per color are still used for the LUT look-up ...
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... There are four SPI Interface signals: SPI_CSX - SPI Chip Select, SPI_SCL - SPI Clock SPI Data In and DO - SPI Data Out. SPI_CSX, SPI_SCL and SPI_DI are inputs on the LM4312. SPI_DO is the Data Output line for the READ_DATA portion of a READ operation. READs are optional and are not required. ...
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... RGB Mode, 0'b= 18-bit RGB Mode Bit 1 - SER_PD 1'b = RESET the SER, 0'b = normal mode Bit[5:4] - Driver Level Select 00’b = VOD = 200mV 01’b = VOD = 150mV na Reserved R/W 0xFF’h enables LM4312 SPI All other values disables LM4312 SPI (0x00 to 0xFE) na Reserved 12 Default 0x00 0x00 0xXX 0x00 0xXX 0x00 ...
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... SPI Timing Figures 14, 15, 16 show a 3–wire SPI Interface with the (LM4312) SPI_DI and (LM4312) SPI_DO pins tied together to form a bi- directional SPI data signal SDA. In the 16–bit READ, the SPI HOST drives the first 8 bits of the operation, and the SPI target (LM4312) drives the last 8 bits as shown in Figure 15 ...
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In Figure 17, 33 host signals are reduced to only signals. The reduced width interface to the display includes: 3 differential signals (DD0, DC, DD1), a Display Driver Reset signal (RSTN) and wire SPI ...
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... RGB transport mode (set by SPI Register). SLEEP MODE & STOP CLOCK The LM4312 (SER) can eneter SLEEP (Low Power state) by two methods. The PD* pin is one method, the other is by stopping the PCLK input (to a static level). ...
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SYSTEM CONSIDERATIONS Typical VGA RGB888 Operation A Smart Display application is shown in Figure 18. The Seri- alizer (SER) resides by the host (BBP) and connects to a Memory Interface. BBP Bus signals are connected as shown (PCLK, Data, DE, ...
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... Impedance should be in the 80 to 100 Ohms for the differential pair. GROUNDING The LM4312 offered in the 48 LLP package uses the center DAP Pad for the Ground connection. This pad MUST be con- nected to Ground for proper device operation. ...
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Connection Diagram 48L LLP Package www.national.com TOP VIEW (not to scale) 18 30011619 ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 48L LLP, 0.4mm pitch Order Number LM4312SM NS Package Number SNF48A 19 www.national.com ...
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... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...