lm4312 National Semiconductor Corporation, lm4312 Datasheet - Page 10

• Manufacturer Part Number: lm4312
• Description: Mobile Pixel Link Two Mpl-2 , Rgb Display Differential Interface Serializer With Optional Dithering And Look Up Table
• Manufacturer: National Semiconductor Corporation

www.national.com
using a high-quality stochastic dithering process. This pro-
cess has a "blue noise" characteristic that minimizes the
visibility of the dither patterns. The resulting data stream of
18-bit data is then serialized and transmitted via MPL-2.
The Dither circuitry requires the VS control signal for
proper operation. This signal is used to generate an internal
signal that marks the start of the (video) frame. The serializer
samples and sends the VS information unmodified.
Dithering parameters are controlled by two registers. When
the dithering is bypassed, only RGB[7:2] is serialized and
transmitted for 18-bit input RGB [5:0] (MSB aligned). Input
RGB[1:0] should not be connected and the unused inputs
should be tied low; do not float. Dithering option is off by
default.
OPTIONAL LOOK UP TABLE
The look up table is comprised of three 256 Byte SRAMs. It
may be used for independent color correction. When the
LM4312 is in the 24-bit RGB mode, the full 8-bits per color are
used for addressing the 256 Bytes for each color. When the
LM4312 is used in an 18-bit RGB mode and the LUT is de-
sired, all 8-bits per color are still used for the LUT look-up. The
6 active bits from each color are used for addressing 64 lo-
cations in the LUT. The two LSBs of the 8-bit bus can be tied
to 00, and every fourth location of the SRAM where the two
LSBs equal 00, (addresses 0x00, 0x04, 0x08, 0x0c, etc.) will
be used." Or, the two LSBs of the 8-bits can be tied to 01 and
every fourth location of the SRAM where the low two bits
equal 01(addresses 0x01, 0x05, 0x09, 0x0d, etc.) will be used
and so on. Selecting the two LSBs with GPIOs (0x0, 0x1, 0x2,
and 0x3) allows for four different color correction tables to be
accessed. The LUT is disabled by default and also after a
device PD* cycle. The PD* cycle can be entered via the PD*
input pin directly, or by stopping the PCLK. When stop PCLK
is used to disable the device, LUT data is retained. Before
using the LUT, the SRAM must be loaded with its contents. If
power is cycled to the device, the LUT must be loaded again.
To enable the LUT:
1.
2.
16-bit READ
The 16-bit READ is shown in 16-bit READ – SPI. The SPI_DI
payload consists of a "1" (Read Command), seven address
bits. The SPI_DO consists of eight data bits which are driven
Select/Unlock the LM4312 SPI Interface - Write 0xFF to
REG 0x16
Write the LUT contents to the SRAM using Writes or
Page Writes
Bit
DI
Bit
DI
DO
B15
0
B15
1
Z
B14
A6
B14
A6
Z
B13
A5
B13
A5
Z
B12
A4
B12
A4
Z
B11
A3
B11
A3
Z
B10
A2
B10
A2
Z
16-bit WRITE – SPI
B9
A1
B9
A1
Z
16-bit READ – SPI
B8
A0
B8
A0
Z
10
3.
4.
When waking up the LM4312 from the power down mode
(PD*=L), the LUT needs to be enabled if it is desired, and the
contents to the SRAM are still held and valid.
1.
2.
3.
4.
If power is cycled to the device, the LUT SRAMs must be
loaded again.
SPI INTERFACE
The Serial Peripheral Interface (SPI) allows control over var-
ious aspects of the LM4312, the Look Up Table operation,
and access to the three 256 x 8-RAM blocks. Three SPI
transactions are supported, which are: 16-bit WRITE, PAGE
WRITE, and a 16-bit READ. The SPI interface is disabled
when the device is in the sleep mode via the PD* pin (PD* =
L). The SPI interface may be used when PD* = H or when the
device is in SLEEP via the PCLK stop feature. A device (SER)
reset function is also available via the Configuration 3 register
bit 1.
Due to the Select/Unlock – De-Select/Lock feature of the de-
vice the SPI interface may be shared with the display driver.
Several connection configurations are possible. A couple ex-
amples are shown in Figure 12 and Figure 13. SPI_DI and
SPI_DO may be tied together to form a bi-directional SDA
line. If READs are not required, leave the SPI_DO pin as a
NC.
16-bit WRITE
The 16-bit WRITE is shown in 16-bit WRITE – SPI. The
SPI_DI payload consists of a "0" (Write Command), seven
address bits and eight data bits. The SPI_CSX signal is driven
Low, and 16-bits of DI (data input) are sent to the device. Data
is latched on the rising edge of the SPI_SCL. After each 16-
bit WRITE, SPI_CSX must return HIGH.
from the device. The SPI_CSX signal is driven Low, and the
host drives the first 8 bits of the DI ("1" and seven address
bits), the device then drives the respective 8 bits of the data
on the DO signal.
B7
D7
B7
Z
D7
Enable the LUT - Write a 0x01 to REG 0x00
De-Select/Lock the LM4312 SPI interface - Write 0x00 to
REG 0x16
Select/Unlock the LM4312 SPI Interface - Write 0xFF to
REG 0x16
Enable the LUT - Write a 0x01 to REG 0x00
Optional -select desired Level Select - if not using default
value
De-Select/Lock the LM4312 SPI interface - Write 0x00 to
REG 0x16
B6
D6
B6
Z
D6
B5
D5
B5
Z
D5
B4
D4
B4
Z
D4
B3
D3
B3
Z
D3
B2
D2
B2
Z
D2
B1
D1
B1
Z
D1
B0
D0
B0
Z
D0