lm4312 National Semiconductor Corporation, lm4312 Datasheet - Page 9

• Manufacturer Part Number: lm4312
• Description: Mobile Pixel Link Two Mpl-2 , Rgb Display Differential Interface Serializer With Optional Dithering And Look Up Table
• Manufacturer: National Semiconductor Corporation

RGB VIDEO INTERFACE
The LM4312 is transparent to data format and control signal
polarity timing. Each PCLK, RGB inputs, HS, VS and DE are
sampled on the rising edge of the PCLK. A PCLK by PCLK
representation of these signals is duplicated on the opposite
device after being transferred across the MPL-2 interface.
The LM4312 can accommodate a wide range of display for-
mats. QVGA to >VGA can be supported within the 5MHz to
30 MHz PCLK input range.
When Dither option is enabled, the 24-bit RGB (R[7:0], G[7:0],
B[7:0]) color information is Dithered to 18 bits, then serialized,
followed by the control bits VS (VSYNC), HS (HSYNC), DE
(Data Enable) and PE (Odd Parity) and Frame Sequence (F
[1:0]) bits. The DC clock is 6X the PCLK, and 24 serial bits
are sent per PCLK
With Dithering disabled, 18-bit RGB (R[7:2], G[7:2], B[7:2])
color information is serialized, followed by the control bits VS
SERIAL PAYLOAD PARITY BIT
Odd Parity is calculated on the RGB bits, control (VS, HS, and
DE) bits and F0, F1 bits and then sent from the SER to the
DES via the serial PE bit. See DES Data sheets to determine
how the parity bit is handled by the DES device.
FRAME SEQUENCE — SYNC DETECT AND RECOVERY
If a data error or clock slip error occurs over the MPL-2 link,
the RGB MPL-2 Deserializer can detect this condition and
quickly recover from it. The method chosen is a data trans-
parent method, and has very little overhead because it does
not use a data expansion coding method. For the 18-bit RGB
color transaction, it uses two bits that are already required in
the 6 DC cycle transaction. Total overhead for each pixel is
3/24 or 12.5%, where the 3 bits are PE, F0 and F1.
The LM4312 MPL-2 RGB Serializer simply increments the
two bit field F[1:0] on every pixel (MPL-2 frame) transmitted.
FIGURE 11. 24-bit dithered to 18-bit RGB / 18-bit RGB, 2 DD + DC Lane Serial Payload (6X)
FIGURE 10. 24-bit RGB, 2 DD + DC Lane Serial Payload (8X)
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Three operating modes of the link are possible (see 2DD+DC
MPL-2 Link Options).
The 24-bit RGB (R[7:0], G[7:0], B[7:0]) color information is
serialized, followed by the control bits VS (VSYNC), HS
(HSYNC), DE (Data Enable) and PE (Odd Parity) and Frame
Sequence (F[1:0]) bits. The DC clock is 8X the PCLK, and 32
serial bits are sent per PCLK. The two additional Reserved
(Low) bits are sent to complete the payload.
(VSYNC), HS (HSYNC), DE (Data Enable) and PE (Odd Par-
ity) and Frame Sequence (F[1:0]) bits. Unused inputs (RGB
[1:0]) must be tied off, do not float. The DC clock is 6X the
PCLK, and 24 serial bits are sent per PCLK.
At a PCLK of 20.8 MHz, a 125 MHz DC clock is generated.
The data lanes use both clock edges, thus 250 Mbps (raw)
are sent per DD lane for a 500Mbps maximum throughput for
the 2DD+DC configuration.
Therefore every four MPL-2 frames, the pattern will repeat. It
is very unlikely that this pattern would be found within the
payload data, and if it were found, the probability that it would
repeat for many frames becomes infinitely small. This code is
used by the MPL-2 Deserializer to detect any frame alignment
problems and quickly recover.
The RGB MPL-2 Deserializer, upon a normal power up se-
quence, uses the FS bits to obtain bit alignment. Once this is
obtained, correct pixel data is recovered and driven to the
display. If synchronization is lost for any reason, the DES
searches for the incrementing pattern. Once found, it resyn-
chronizes the output pixel data and timing signals. See MPL-2
DES Datasheet for details on how the specific DES handles
the Frame Sequence.
OPTIONAL DITHERING FEATURE
The LM4312 provides an optional Dithering mode. When se-
lected, 24-bit RGB input data is internally dithered to 18-bits
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