ad9381-pcbz Analog Devices, Inc., ad9381-pcbz Datasheet
ad9381-pcbz
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ad9381-pcbz Summary of contents
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... RTERM DDCSDA HDCP HDCP KEYS DDCSCL Figure 1. Fabricated in an advanced CMOS process, the AD9381 is provided in a space-saving, 100-lead, surface-mount, Pb-free plastic LQFP and is specified over the 0°C to 70°C temperature range. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 © ...
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... AD9381 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Digital Interface Electrical Characteristics ............................... 3 Absolute Maximum Ratings............................................................ 5 Explanation of Test Levels ........................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Design Guide..................................................................................... 9 General Description..................................................................... 9 Digital Inputs ................................................................................ 9 Serial Control Port ....................................................................... 9 Output Signal Handling............................................................... 9 Timing ...
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... DD − 0.1 0 700 75 3.3 3.47 3.15 3.3 3.3 347 1.7 3.3 1.8 1.9 1.7 1.8 1.8 1.9 1.7 1.8 80 100 100 55 AD9381 Max Unit V 0.8 V μA μ 0 °C/W Max Unit Bit 700 mV 3.47 V 347 V 1.9 V 1.9 V 110 mA 3 175 mA ...
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... L IV Output drive = low Output drive = high Output drive = low –0 Rev Page AD9381KSTZ-100 AD9381KSTZ-150 Typ Max Min Typ 88 110 110 130 130 +2.0 –0.5 50 Max Unit 145 360 ps ...
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... Rev Page Test 100% production tested. 100% production tested at 25°C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C; guaranteed by design and characterization testing. AD9381 ...
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... DIGITAL VIDEO CLOCK INPUTS 43 44 OUTPUTS PIN 1 AD9381 TOP VIEW (Not to Scale) Figure 2. Pin Configuration Mnemonic Function PWRDN Power-Down Control Rx0+ Digital Input Channel 0 True Rx0− Digital Input Channel 0 Complement Rx1+ Digital Input Channel 1 True Rx1− ...
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... External Reference Audio Clock In MCLKOUT Audio Master Clock Output SCLK Audio Serial Clock Output LRCLK Data Output Clock for Left and Right Audio Channels DE Data Enable RTERM Sets Internal Termination Resistance Rev Page AD9381 Value PV DD 3 3.3 V 1 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3 ...
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... DD This supplies power to the digital logic. GND Ground. The ground return for all circuitry on chip recommended that the AD9381 be assembled on a single solid ground plane, with careful attention to ground current paths. 1 The supplies should be sequenced such that V may be connected to a lower supply voltage (as low as 1.8 V) for compatibility. ...
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... OUTPUT SIGNAL HANDLING The digital outputs operate from 1 3 Power Management The AD9381 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down pin to determine the correct power state. There are four power states: full-power, seek mode, auto power-down, and power-down ...
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... DE GENERATOR The AD9381 has an onboard generator for DE, for start of active video (SAV) and for end of active video (EAV), all of which is necessary for describing the complete data stream for a BT656-compatible output ...
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... TO 4:2:2 FILTER The AD9381 contains a filter that allows it to convert a signal from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the maximum accuracy and fidelity of the original signal. Input Color Space to Output Color Space The AD9381 can accept a wide variety of input formats and either retain that format or convert to another. Input formats supported are: • ...
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... AD9381 AUDIO PLL SETUP Data contained in the audio infoframes, among other registers, define for the AD9381 HDMI receiver not only the type of audio, but the sampling frequency (f ). The audio infoframe also S contains information about the N and CTS values used to recreate the clock. With this information it is possible to regenerate the audio sampling frequency ...
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... These modes and the pin mapping are shown in Table 10. . Green Green/Y [7:0] Y [7:0] ↑ ↑ B [7:4] DDR B [3:0] DDR 4:2:2 ↓ DDR G [7:4] DDR 4:2:2 Y [11:0] Rev Page Blue Blue/Cb [7:0] ↑ ↓ DDR 4:2:2 CbCr Y, Y ↑ CbCr [11:0] ↓ Y,Y [11:0] AD9381 ...
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... AD9381 2-WIRE SERIAL REGISTER MAP The AD9381 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 11. Control Register Map Hex Read/Write Address or Read Only ...
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... HDCP A0 **0***** MCLK External Enable ***0**** BT656 EN ****0*** Force DE Generation Rev Page AD9381 Description Output field polarity active low out active high out don’t invert clock out invert clock out. Selects which clock to use on output pin. 1× CLK is divided down from TMDS clock input when pixel repetition is in use ½ ...
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... AD9381 Hex Read/Write Address or Read Only Bits [2:0] 0x28 Read/Write [7:2] [1:0] 0x29 Read/Write [7:0] 0x2A Read/Write [3:0] 0x2B Read/Write [7:0] 0x2C Read/Write [3:0] 0x2D Read/Write [7:0] 0x2E Read/Write [7] [6:5] [4:0] 0x2F Read [6] [5] [4] [3] [2:0] 0x30 Read [6] [5] [4] [3:0] 0x31 Read/Write [7:4] [3:0] 0x32 Read/Write [7] [6] [5:0] 0x33 Read/Write [7] [6] [5:0] 0x34 Read/Write [7:6] [5] Default Value Register Name ...
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... CSC_Coeff_B2 ***11110 CSC_Coeff_B3 MSB 10001001 CSC_Coeff_B3 LSB Rev Page AD9381 Description Allows the previous bit to be used to set low frequency mode rather than the internal auto- detect repeat Cr and Cb values interpolate Cr and Cb values. Enables the FIR filter for 4:2:2 CrCb output. ...
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... AD9381 Hex Read/Write Address or Read Only Bits 0x43 Read/Write [4:0] 0x44 Read/Write [7:0] 0x45 Read/Write [4:0] 0x46 Read/Write [7:0] 0x47 Read/Write [4:0] 0x48 Read/Write [7:0] 0x49 Read/Write [4:0] 0x4A Read/Write [7:0] 0x4B Read/Write [4:0] 0x4C Read/Write [7:0] 0x50 Read/Write [7:0] 0x56 Read/Write [7:0] 0x57 Read/Write [7] [6] [3] [2] 0x58 Read/Write [7] [6:4] [3] [2:0] 0x59 Read/Write [6] [5] ...
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... Audio Channel Status Channel Status Category Code Channel Number Source Number Clock Accuracy Sampling Frequency Rev Page AD9381 Description These 7 bits are updated if any specific packet has been received since last reset or loss of clock detect. Normal is 0x00. Bit Data Packet Detected 0 AVI infoframe ...
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... AD9381 Hex Read/Write Address or Read Only Bits 0x62 Read [3:0] 0x7B Read [7:0] 0x7C Read [7:0] 0x7D Read [7:4] Read [3:0] 0x7E Read [7:0] 0x7F Read [7:0] 0x80 Read [7:0] 0x81 Read [6:5] 4 [3:2] [1:0] 0x82 Read [7:6] [5:4] Default Value Register Name Word Length CTS [19:12] CTS [11:4] CTS [3:0] N [19:16] N [15:8] N [7:0] AVI Infoframe AVI Infoframe Version ...
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... Active Line End LSB Active Line End MSB Active Pixel Start LSB Active Pixel Start MSB Active Pixel End LSB Active Pixel End MSB New Data Flags Rev Page AD9381 Description R [3:0]. 1000 = same as picture aspect ratio. 1001 = 4:3 (center). 1010 = 16:9 (center). 1011 = 14:9 (center). SC [1:0]. ...
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... AD9381 Hex Read/Write Address or Read Only Bits 0x90 Read [7:0] 0x91 Read [7:4] [2:0] 0x92 Read [4:2] [1:0] 0x93 Read [7:0] 0x94 Read [7:0] 0x95 Read 7 [6:3] 0x96 Read [7:0] 0x97 Read [6:0] Default Value Register Name Audio Infoframe Version Audio Coding Type Audio Coding Count Sampling Frequency Sample Size Max Bit Rate ...
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... New Data Flags PD13 PD14 PD15 PD16 Source Device Information Code New Data Flags Rev Page AD9381 Description Vendor name character 1 (VN1) 7-bit ASCII code. The first character in 8 that is the name of the company that appears on the product. VN2. VN3. VN4. VN5. ...
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... AD9381 Hex Read/Write Address or Read Only Bits 0xB8 Read [7:0] 0xB9 Read [7:0] 0xBA Read [7:0] 0xBB Read [7:0] 0xBC Read [7:0] 4 0xBD Read [1:0] 0xBE Read [7:0] 0xBF Read [6:0] 0xC0 Read [7:0] 0xC1 Read [7:0] 0xC2 Read [7:0] 0xC3 Read [7:0] 0xC4 Read [7:0] 0xC5 Rea [7:0] 0xC6 Read [7:0] 0xC7 Read [6:0] 0xC8 7 Read ...
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... ISRC2_PB6 ISRC2_PB7 ISRC2_PB8 ISRC2_PB9 New Data Flags ISRC2_PB10 ISRC2_PB11 ISRC2_PB12 ISRC2_PB13 ISRC2_PB14 ISRC2_PB15 ISRC2_PB16 Rev Page AD9381 Description ISRC1_PB8. ISRC1_PB9. ISRC1_PB10. ISRC1_PB11. ISRC1_PB12. New data flags (see 0x87). ISRC1_PB13. ISRC1_PB14. ISRC1_PB15. ISRC1_PB16. ISRC2 Packet Byte 0 (ISRC2_PB0). This is transmitted only when the ISRC_ continue bit (Register 0xC8, Bit 7) is set to 1 ...
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... AD9381 2-WIRE SERIAL CONTROL REGISTER DETAILS CHIP IDENTIFICATION 0x00—Bits[7:0] Chip Revision An 8-bit value that reflects the current chip revision. 0x11—Bit[7] HSYNC Source 0 = HSYNC SOG. The power-up default is 0. These selections are ignored if Register 0x11, Bit 0x11—Bit[6] HSYNC Source Override 0 = auto HSYNC source manual HSYNC source ...
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... An 8-bit register that sets the duration of the HSYNC output pulse. The leading edge of the HSYNC output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9381 then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the HSYNC output, which is also phase-adjusted. The power-up default is 32. 0x24— ...
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... AD9381 0x26—Bit[7] Output Three-State When enabled, this bit puts all outputs (except SOGOUT high impedance state normal outputs all outputs (except SOGOUT) in high impedance mode. The power-up default setting is 0. 0x26—Bit[5] S/PDIF Three-State When enabled, this bit places the S/PDIF audio output pins in a high impedance state ...
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... Macrovision Line Count Start Set the start line for Macrovision detection. Along with Register 0x33, Bits [5:0], they define the region where MV pulses are expected to occur. The power-up default is Line 13. Rev Page AD9381 Repetition Multiplier 1× 2× 3× 4× ...
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... AD9381 0x33—Bit[7] Macrovision Detect Mode 0 = standard definition progressive scan mode. 0x33—Bit[6] Macrovision Settings Override This defines whether preset values are used for the MV line counts and pulse widths or the values stored use hard-coded settings for line counts and pulse widths. ...
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... Normal is 0x00. Table 20. Packet Detect Bit 0x5B—Bit[3] HDMI Mode 0 = DVI HDMI. Rev Page AD9381 _N S used for MCLK out Multiple S 128 256 384 512 640 768 ...
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... AD9381 0x5E—Bits[7:6] Channel Status Mode 0x5E—Bits[5:3] PCM Audio Data 0x5E—Bit[2] Copyright Information 0x5E—Bit[1] Linear PCM Identification 0x5E—Bit[0] Use of Channel Status Block 0x5F—Bits[7:0] Channel Status Category Code 0x60—Bits[7:4] Channel Number 0x60—Bits[3:0] Source Number 0x61—Bits[5:4] Clock Accuracy 0x61— ...
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... Abbreviation FCL FCR RCL RCR LFE Rev Page AD9381 Speaker Placement Front left Front center Front right Front center left Front center right Rear left Rear center Rear right Rear center left Rear center right Low frequency effect ...
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... AD9381 Table 33. CA Bit 4 Bit 3 Bit 2 Bit 1 Bit ...
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... These bits define where in the ISRC track the samples are: at least two transmissions of 001 occur at the beginning of the track, while continuous transmission of 010 occurs in the middle of the track, followed by at least two transmissions of 100 near the end of the track. Rev Page AD9381 ...
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... AD9381 0xC9—Bits[7:0] ISRC1 Packet Byte 0 (ISRC1_PB0) 0xCA—Bits[7:0] ISRC1_PB1 0xCB—Bits[7:0] ISRC1_PB2 0xCC—Bits[7:0] ISRC1_PB3 0xCD—Bits[7:0] ISRC1_PB4 0xCE—Bits[7:0] ISRC1_PB5 0xCF—Bits[6:0] New Data Flags See Register 0x87 for a description. 0xD0—Bits[7:0] ISRC1_PB6 0xD1—Bits[7:0] ISRC1_PB7 0xD2—Bits[7:0] ISRC1_PB8 0xD3— ...
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... Any base address higher than the maximum value does not produce an acknowledge signal. Data are read from the control registers of the AD9381 in a similar manner. Reading requires two data transfer operations: • The base address must be written with the R/ slave address byte low to set up a sequential read operation ...
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... AD9381 SERIAL INTERFACE READ/WRITE EXAMPLES Write to one control register: • Start signal • Slave address byte (R/ W bit = low) • Base address byte • Data byte to base address • Stop signal Write to four consecutive control registers: • Start signal • Slave address byte (R/ W bit = low) • ...
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... Adding a series resistor of value 50 Ω to 200 Ω can suppress reflections, reduce EMI, and reduce the current spikes inside the AD9381. If series resistors are used, place them as close as possible to the AD9381 pins (although try not to add vias or extra length to the output trace to move the resistors closer). ...
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... AD9381 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 38. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9381) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x0C 0x52 Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x1C 0x54 Register Blue/Cb Coeff 1 Address ...
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... Green/Y Coeff 3 0x3F 0x40 0x41 0x08 0x11 0x01 Blue/Cb Coeff 2 Blue/Cb Coeff 3 0x47 0x48 0x49 0x1B 0x57 0x07 Rev Page AD9381 Red/Cr Offset 0x3A 0x3B 0x3C 0x3F 0x08 0x00 Green/Y Offset 0x42 0x43 0x44 0x27 0x00 0x00 Blue/Cb Offset 0x4A ...
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... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Max Speed (MHz) Model Analog Digital 1 AD9381KSTZ-100 100 100 1 AD9381KSTZ-150 150 150 AD9381/PCB Pb-free part. 1.60 MAX 0.75 100 1 0.60 0.45 PIN 1 TOP VIEW (PINS DOWN) 0.20 0.09 7° 3.5° 25 0° 26 0.08 MAX COPLANARITY VIEW A 0.50 BSC ...
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... NOTES Rev Page AD9381 ...
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... AD9381 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05689-0-10/05(0) Rev Page ...