w83627ef Winbond Electronics Corp America, w83627ef Datasheet
w83627ef
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w83627ef Summary of contents
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W83627EHF/EF W83627EHG/EG WINBOND LPC I/O Date : November/16/2006 Revision :1.3 ...
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... N/A Correct typo at 5.11. 1. Correct DC CHARACTERISTICS description 0.52 N/A 2. Update Demo Circuit 3. Add Pb-free part no:W83627EHG 0.6 N/A Add SMART FAN 0.61 N/A Update application circuit Add new part W83627EF and 0.62 N/A W83627EG. Update pin configuration and 0.63 N/A application circuit Correct information and add AC Power 1.0 N/A Loss Timing chart 1.1 N/A Correct LPT function pins description. ...
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Table of Contents- 1. GENERAL DESCRIPTION ............................................................................................................... 1 2. FEATURES....................................................................................................................................... 2 3. BLOCK DIAGRAM ............................................................................................................................ 5 4. PIN CONFIGURATION..................................................................................................................... 7 5. PIN DESCRIPTION .......................................................................................................................... 9 5.1 LPC Interface .......................................................................................................................... 9 5.2 FDC Interface ........................................................................................................................ 10 5.3 Multi-Mode Parallel Port........................................................................................................ 11 ...
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SMI# interrupt mode.............................................................................................................. 38 6.6.1 Voltage SMI# mode ...................................................................................................................38 6.6.2 Fan SMI# mode .........................................................................................................................38 6.6.3 Temperature SMI# mode...........................................................................................................39 6.7 OVT# interrupt mode............................................................................................................. 41 6.8 Registers and RAM ............................................................................................................... 42 6.8.1 Address Port (Port x5h) .............................................................................................................42 6.8.2 Data Port (Port ...
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SMI# Mask Register 2 - Index 44h (Bank 0) .............................................................................64 6.8.37 Reserved Register - Index 45h (Bank 0)..................................................................................64 6.8.38 SMI# Mask Register 3 - Index 46h (Bank 0) .............................................................................64 6.8.39 Fan Divisor Register I - Index 47h (Bank 0)..............................................................................65 ...
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Interrupt Status Register 3 - Index 50h (Bank 4) .......................................................................85 6.8.82 SMI# Mask Register 4 - Index 51h (Bank 4) ..............................................................................86 6.8.83 Reserved Register - Index 52h (Bank 4)....................................................................................87 6.8.84 BEEP Control Register 3 - Index 53h (Bank 4)..........................................................................87 ...
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GENERAL DESCRIPTION W83627EHF/EHG/EF/ evolving product from Winbond's most popular I/O family. feature a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the new generation chip-set. This interface as its name suggests ...
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FEATURES General • Meet LPC Spec. 1.01 • Support LDRQ#(LPC DMA), SERIRQ (Serial IRQ) • Integrated Hardware Monitor functions • Compliant with Microsoft PC2000/PC2001 Hardware Design Guide • Support DPM (Device Power Management), ACPI • Programmable configuration settings • ...
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Programmable baud rate generator allows division of 1.8461 MHz and 24 MHz (216-1) • Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz Infrared • Support IrDA version 1.0 ...
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General Purpose I/O Ports • 48 programmable general purpose I/O ports • GPIO port 1 and 4 can not only serve as simple I/O ports but also watch dog timer output, Power LED output, Suspend LED output • Functional in ...
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BLOCK DIAGRAM LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Joystick interface signals MSI MSO General-purpose I/O pins Hardware monitor channel and Vref Keyboard/Mouse data and clock W83627EHF/EF, W83627EHG/EG LPC Interface FDC Game Port URA, B MIDI GPIO PRT HM ACPI ...
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... LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Joystick interface signals MSI MSO General-purpose I/O pins Keyboard/Mouse data and clock W83627EHF/EF, W83627EHG/EG LPC Interface FDC Game Port URA, B MIDI IR GPIO PRT KBC ACPI W83627EF/ Floppy drive interface signals Serial port A, B interface signals IRRX IRTX Printer port interface signals ...
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PIN CONFIGURATION CPUTIN 103 SYSTIN 104 VID5 105 VID4 106 VID3 107 VID2 108 VID1 109 VID0 110 AUXFANIN0 111 CPUFANIN0 112 SYSFANIN 113 AVCC 114 CPUFANOUT0 115 SYSFANOUT 116 AGND 117 BEEP#/(SO) 118 GP21/CPUFANIN1/MSI 119 GP20/CPUFANOUT1/MSO 120 GP17/GPSA2 ...
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... NC 103 NC 104 NC 105 NC 106 NC 107 NC 108 NC 109 NC 110 NC 111 NC 112 NC 113 3VCC 114 W83627EF/EG NC 115 NC 116 VSS 117 SO 118 GP21/MSI 119 GP20/MSO 120 GP17/GPSA2 121 GP16/GPSB2 122 GP15/GPY1 123 GP14/GPY2 124 GP13/GPX2 125 GP12/GPX1 126 GP11/GPSB1 127 GP10/GPSA1 128 W83627EHF/EF, W83627EHG/EG ...
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PIN DESCRIPTION Note: Please refer to Section 8.2 DC CHARACTERISTICS for details. AOUT - Analog output pin AIN - Analog input pin IN - CMOS level Schmitt-triggered input pin TTL level input pin ...
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FDC Interface SYMBOL PIN I/O DRVDEN0 1 OD Drive Density Select bit 0. 24 This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index ...
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Multi-Mode Parallel Port SYMBOL PIN I/O IN SLCT BUSY ACK ERR OUT SLIN INIT# 44 OUT / OD ...
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Multi-Mode Parallel Port, continued. SYMBOL PIN I/O I/O PD1 41 12ts I/O PD2 40 12ts I/O PD3 39 12ts I/O PD4 38 12ts I/O PD5 37 12ts I/O PD6 36 12ts I/O PD7 35 12ts 5.4 Serial Port & Infrared ...
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Serial Port & Infrared Port Interface, Continued. PIN SYMBOL I/O IN DSRB I/OD GP46* 12t OUT RTSA# IN HEFRAS t 51 I/O GP65 8 OUT RTSB# 80 I/OD GP45*** OUT DTRA PENROM I/O GP64 8 ...
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Serial Port & Infrared Port Interface, Continued. SYMBOL PIN I/O OUT SOUTA 54 IN PENKBC t I/O GP62 8 SOUTB OUT 83 IRTX I/OD GP42* IN DCDA I/OD GP61 IN DCDB I/OD GP41*** IN RIA# 57 ...
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KBC Interface SYMBOL PIN I/O GA20M 59 OUT KBRST 60 OUT KCLK I/OD 62 GP27 I/OD KDAT I/OD 63 GP26 I/OD MCLK I/OD 65 GP25 I/OD MDAT I/OD 66 GP24 I/OD 5.6 Serial Flash Interface SYMBOL PIN I/O SCE# ...
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... This signal can be latched if pin VBAT is connect to battery, even t W83627EHF/EHG is power off. This pin is VSS for W83627EF/EG.Pull down is recommended if (For H version only, C version is falling edge trigger only 2.048V FSR Analog Inputs. (FSR: Full Scale Register 2.048V FSR Analog Inputs. ...
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Hardware Monitor Interface, continued. SYMBOL PIN I/O AUXFANIN0 111 CPUFANIN0 112 I/O SYSFANIN 113 CPUFANIN1 I/O 119 IN MSI GP21 I/OD AUXFANOUT 7 AOUT/ CPUFANOUT0 115 OD SYSFANOUT 116 AOUT/ CPUFANOUT1 OUT 120 MSO OUT GP20 I/OD 5.8 Game Port ...
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Game Port & MIDI Port, continued. SYMBOL PIN GPY2 I/OD 124 GP14* GPY1 I/OD 123 GP15** GPSB2 122 I/OD GP16* GPSA2 121 I/OD GP17** MSI 119 CPUFANIN1 I/O GP21 I/OD MSO OUT AOUT/ CPUFANOUT1 120 OUT GP20 I/OD Note. The ...
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ACPI Interface SYMBOL PIN I/O PSIN IN 68 GP56 I/OD PSOUT GP57 I/OD VBAT 74 PWR RSTOUT0 RSTOUT1# 93 OUT RSTOUT2# OUT 90 GP32 I/OD SCL IN RSTOUT3# OUT 89 GP33 I/OD SDA I/OD RSTOUT4# ...
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GPIO-2 Interface SYMBOL PIN GP20 I/OD AOUT/ CPUFANOUT1 120 OUT MSO OUT GP21 I/OD CPUFANIN1 I/O 119 IN MSI GP22 I/OD 19 SCE# OUT GP23 I/OD 2 SCK OUT GP24 I/OD 66 MDAT I/OD GP25 I/OD 65 MCLK I/OD ...
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GPIO-3 Interface SYMBOL PIN I/O GP30 92 I/OD 12t GP31 91 I/OD 12t GP32 I/OD 12t 90 RSTOUT2# OUT SCL IN ts GP33 I/OD 12t RSTOUT3# 89 OUT SDA I/OD 12ts GP34 I/OD 12t 88 RSTOUT4# OUT GP35 87 ...
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GPIO-5 Interface, continued. SYMBOL PIN I/O GP55 I/O 12t 70 SUSLED OUT GP56 I/OD 12t 68 PSIN IN td GP57 I/OD 12t 67 PSOUT 5.10.7 GPIO-6 Interface see 5.4 Serial Port A 5.10.8 GPIO-1 and GPIO-4 with WDTO# ...
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Hardware monitor 6.1 General Description The W83627EHF/EHG can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high- end computer system to work ...
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LPC Bus Port 5h Index Register Port 6h Data Register Figure 6.1 : LPC interface access diagram W83627EHF/EF, W83627EHG/EG Smart Fan Configuration Registers 00h-1Fh Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# Mask Registers 43h-44h Fan Divisor Register I ...
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I C interface 2 The second interface uses I C Serial Bus. W83627EHF/EHG has a programmable serial bus address. It defined at Index 48h. 2 6.2.2.1. Serial bus (I C) access timing (a) Serial bus write to internal ...
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V0 Positive Voltage Input V1 Negative Voltage Input R THM 10K@25 C, beta=3435K 6.3.1 Monitor over 2.048V voltage The +12V input voltage can be expressed as following equation. The value of R1 and R2 can be selected to 56K Ohms ...
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W83627EHF/EHG and the second function is that this voltage with 3.3V is connected to internal serial resistors to monitor the +3.3V voltage. The W83627EHF/EHG internal two serial resistors are 34 KΩ and 34 KΩ so that input voltage to ADC ...
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Monitor temperature from thermistor The W83627EHF/EHG can connect three thermistors to measure three different environment temperature. The specification of thermistor should be considered to (1) β value is 3435K, (2) resistor value is 10K ohms at 25°C. In the ...
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The default divisor is 2 and defined at Bank0 Index 47h.bit7~4, Index 4Bh.bit7~6, Index 4Ch.bit7, Index 59h.bit7.bit3~2 and Index 5Dh.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed ...
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Smart Fan Control TM SMART FAN I： Smart Fan Control provides two mechanisms. One is Thermal Cruise mode and the other is Fan Speed Cruise mode. When enable Smart Fan, the Fan output will start from previous setting of ...
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One more protection is provided that Fan output will not be decreased the above (3) situation in order to keep the fans running with a minimum speed. By setting Bank0 Index12h.bit3 Fan output will be ...
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Fan Speed Cruise mode There are 4 pairs of Fan input/Fan output control at this mode: SYSFANIN with SYSFANOUT, CPUFANIN0 with CPUFANOUT0, AUXFANIN with AUXFANOUT and CPUFANIN1 with CPUFANOUT1. At this mode, W83627EHF/EHG provides the Smart Fan system which ...
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Table 6.3-1 Display Register- at Smart Fan I Mode REGISTER DESCRIPTION ADDRESS Bank1 Current CPU Temperature 50H ,51H Bank 0 Current SYS Temperature 27H Bank2 Current AUX Temperature 50H,51H Current Bank0 CPUFANOUT0 03H Output Value Current Bank0 SYSFANOUT 01H Output ...
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Table 6.3-3 Relative Register-at Speed Cruise Mode of Smart Fan I control mode THERMAL- TARGET-SPEED CRUISE MODE COUNT SYSFANOUT CR[05h] CPUFANOUT0 CR[06h] AUXFANOUT0 CR[13h] CPUFANOUT1 CR[63h] TM SMART FAN III Concept TM SMART FAN III mode sets a target temperature ...
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Temperature Tolerance), which is shown in Figure 6.10, fan speed jumps up to the next step. “Step” here refers to the value in the CPUFANOUT Output Value Select Register, Bank0 Index03h or Index61h. (3) Meanwhile, original Target Temperature dynamically shifts ...
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Fan output Fan output Fan output (DC / PWM) (DC / PWM) (DC / PWM) Max. Fan Output Max. Fan Output Max. Fan Output Min. Fan Output Min. Fan Output Min. Fan Output Tar. - Tol. Tar. - Tol. Tar. ...
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Current Temp. < Target Temp. - Tol. Current Temp. < Target Temp. - Tol. Fan output Fan output (DC / PWM) (DC / PWM) Max. Fan Output Max. Fan Output Fan Initial Fan Initial Output Value Output Value Step Step ...
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Table 6.4-2 Relative Register-at Smart Fan III control mode SMART-FAN III TARGET MODE TEMPERATURE CPUFANOUT0 CR[06h] CPUFANOUT1 CR[63h] Smart-Fan III Mode Output Step Step Down Time Step Up Time CPUFANOUT0 CR[68h] CPUFANOUT1 CR[6Ah] 6.6 SMI# interrupt mode The HM_SMI#/OVT# pin ...
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Temperature SMI# mode 6.6.3.1. Temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes (1) Comparator Interrupt Mode Setting the T (Temperature Hysteresis) limit to 127°C will set temperature sensor 1 SMI# to HYST the Comparator Interrupt Mode. Temperature exceeds T ...
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HYST SMI# *Interrupt Reset when Interrupt Status Registers are read 6.6.3.2. Temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes It is programmed at Bank0 Index 4Ch.bit 6. (1) Comparator Interrupt Mode Temperature exceeding T ...
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OVT# interrupt mode The HM_SMI#/OVT# pin (pin multi-function pin. The function is selected at Configuration Register CR[29h] bit 6. The OVT# mode selection bits are at Bank0 Index18h bit4, Bank1 Index 52h bit1 and Bank2 Index ...
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Registers and RAM Address Port and Data Port are set in the register CR60 and CR61 of Device B which is Hardware Monitor Device. The value in CR60 is high byte and that in CR61 is low byte. For ...
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SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0) Register Location: Power on Default Value: Attribute: Size The register is meaningful when SYSFANOUT be programmed as PWM output. Bit 7: SYSFANOUT PWM Input Clock Source ...
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SYSFANOUT Output Value Select Register - Index 01h (Bank 0) Register Location: Power on Default Value: Attribute: Size (1)If SYSFANOUT be programmed as PWM output (Bank0 Index 04h.bit0 is 0) Bit 7-0: SYSFANOUT PWM Duty Cycle. Write ...
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If AVCC= 3.3V , output voltage table is BIT 7 BIT 6 BIT 5 BIT 4 BIT ...
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Continued. BIT 7 BIT 6 BIT 5 BIT 4 BIT ...
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Bit 6-0: CPUFANOUT0 PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is ...
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FAN Configuration Register I - Index 04h (Bank 0) Register Location: Power on Default Value: Attribute: Size Bit 7-6: Reserved Bit 5-4: CPUFANOUT0 mode control. Set 00, CPUFANOUT0 is as Manual Mode. (Default). Set 01, CPUFANOUT0 is ...
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Thermal Cruise mode: Bit 7: Reserved. Bit 6-0: SYSTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 7-0: SYSFANIN Target Speed. 6.8.9 CPUTIN Target Temperature Register/ CPUFANIN0 Target Speed Register - Index 06h ...
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Tolerance of Target Temperature or Target Speed Register - Index 07h (Bank 0) Register Location: Power on Default Value: Attribute: Size (1)When at Thermal Cruise mode or Bit 7-4: Tolerance of CPUTIN Target Temperature. Bit ...
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CPUFANOUT0 Stop Value Register - Index 09h (Bank 0) Register Location: Power on Default Value: Attribute: Size When at Thermal Cruise mode or value. This register should be written a non-zero minimum stop value. Please note ...
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CPUFANOUT0 Start-up Value Register - Index 0Bh (Bank 0) Register Location: Power on Default Value: Attribute: Size When at Thermal Cruise mode, CPUFANOUT0 value will increase from 0 to this register value to provide a minimum ...
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CPUFANOUT0 Stop Time Register - Index 0Dh (Bank 0) Register Location: Power on Default Value: Attribute: Size When at Thermal Cruise mode or CPUFANOUT0 value is from stop value to 0. (1)When at PWM output: The ...
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Fan Output Step Up Time Register - Index 0Fh (Bank 0) Register Location: Power on Default Value: Attribute: Size This register determines the speed of FANOUT increasing the its value in Smart Fan Control mode. (1)When ...
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Bit 6-0: AUXFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is ...
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FAN Configuration Register II - Index 12h (Bank 0) Register Location: Power on Default Value: Attribute: Size Bit 7: Reserved Bit 6: Set 1, CPUFANOUT1 value will decrease to and keep the value set in Index ...
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AUXTIN Target Temperature Register/ AUXFANIN0 Target Speed Register - Index 13h (Bank 0) Register Location: Power on Default Value: Attribute: Size (1)When at Thermal Cruise mode: Bit 7: Reserved. Bit 6-0: AUXTIN Target Temperature. (2)When ...
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AUXFANOUT Stop Value Register - Index 15h (Bank 0) Register Location: Power on Default Value: Attribute: Size When at Thermal Cruise mode, AUXFANOUT value will decrease to this value. This register should be written a non-zero ...
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AUXFANOUT Stop Time Register - Index 17h (Bank 0) Register Location: Power on Default Value: Attribute: Size When at Thermal Cruise mode, this register determines the time of which AUXFANOUT value is from stop value to ...
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Reserved - Index 19h (Bank 0) 6.8.29 Reserved - Index 1A-1Bh (Bank 0) 6.8.30 Reserved - Index 1Ch-1Fh (Bank 0) 6.8.31 Value RAM ⎯ Index 20h- 3Fh (Bank 0) ADDRESS A6-A0 20h CPUVCORE reading 21h VIN0 reading 22h AVCC ...
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Continued. ADDRESS A6-A0 37h VIN3 High Limit 38h VIN3 Low Limit 39h SYSTIN temperature sensor High Limit 3Ah SYSTIN temperature sensor Hysteresis Limit SYSFANIN Fan Count Limit 3Bh Note the number of counts of the internal clock for ...
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Bit 4: Reserved Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Bit 2: Reserved Bit 1: A one enables ...
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Bit 7: A one indicates that the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFan Bit 6: A one indicates that the SYSTIN temperature has been ...
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SMI# Mask Register 2 - Index 44h (Bank 0) Register Location: Power on Default Value: Attribute: Size: 7 Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. 6.8.37 Reserved Register - Index 45h (Bank 0) ...
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Fan Divisor Register I - Index 47h (Bank 0) Register Location: Power on Default Value: Attribute: Size Bit 7-6: CPUFANIN0 Divisor bit1:0. Bit 5-4: SYSFANIN Divisor bit1:0. Bit 3: CPUFANIN1 output value if bit 0 sets to ...
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Reserved - Index 49h (Bank 0) 6.8.42 CPUFANOUT1 with Temperature source Select - Index 4Ah (Bank 0) Register Location: Power on Default Value: Attribute: Size Bit 7-2: Reserved. Bit 1-0: Select Temperature source for CPUFANOUT1 at Thermal ...
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Bit 5-4: Select A/D Converter Clock Input. <5:4> default. ADC clock select 22.5 Khz. <5:4> = 01- ADC clock select 5.6 Khz. (22.5K/4) <5:4> ADC clock select 1.4Khz. (22.5K/16) <5:4> ADC ...
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Bit 7-6: Reserved. Bit 5: AUXFANIN0 output value if bit 4 sets to 0. Write 1, pin111(AUXFANIN0) always generates a logic high signal. Write 0, pin111 always generates a logic low signal. This bit is default 0. Bit 4: ...
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Bit 5: BEEP output control for AUXFANIN1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 4: BEEP output control for CPUFANIN1 if the monitor value ...
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Bit 7: BEEP output control for CPUFANIN0 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 6: BEEP output control for SYSFANIN if the monitor value ...
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Bit 0: BEEP output control for VIN1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. 6.8.51 Chip ID - Index 58h (Bank 0) Register Location: Power ...
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Reserved - Index 5Ah-5Ch (Bank 0) 6.8.54 VBAT Monitor Control Register - Index 5Dh (Bank 0) Register Location: Power on Default Value: Attribute: Size Bit 7: AUXFANIN0 Divisor bit2. Bit 6: CPUFANIN0 Divisor bit2. Bit 5: SYSFANIN ...
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Reserved Register - Index 5Eh-5Fh (Bank 0) 6.8.56 CPUFANOUT1 PWM Output Frequency Configuration Register - Index 60h (Bank 0) Register Location: Power on Default Value: Attribute: Size The register is meaningful when CPUFANOUT1 be programmed as PWM ...
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CPUFANOUT1 be programmed as PWM output (Bank0 Index 62h.bit6 is 0) Bit 7-0: CPUFANOUT1 PWM Duty Cycle. Write FFh, CPUFANOUT1 duty cycle is 100%. Write 00h, CPUFANOUT1 duty cycle is 0%. Note. XXh: PWM Duty Cycle output ...
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Bit 5-4: CPUFANOUT1 mode control. Set 00, CPUFANOUT1 is as Manual Mode. (Default). Set 01, CPUFANOUT1 is as Thermal Cruise Mode. Set 10, CPUFANOUT1 is as Fan Speed Cruise Mode. Set 11, CPUFANOUT1 is SMART FAN (1)When at Thermal Cruise ...
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When at Thermal Cruise mode or value. This register should be written a non-zero minimum stop value. Please note that Stop Value does not mean that fan really stops. It means that if the temperature keeps below ...
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When at Thermal Cruise mode or CPUFANOUT1 value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: ...
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This register determines the value that CPUFANOUT0 in SMART FAN increased to the next speed. 6.8.65 CPUFANOUT1 Maximum Output Value Register - Index 69h (Bank 0) Register Location: Power on Default Value: Attribute: Size ...
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CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1) Register Location: 50h Attribute: Read Only Size: 8 bits Bit 7-0: Temperature <8:1> of CPUTIN sensor, which is high byte, means 1 6.8.68 CPUTIN ...
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CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1) Register Location: Power on Default Value: Size: 7 Bit 7-5: Read Only - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to ...
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CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) Register Location: Power on Default Value: Attribute: Size: 7 Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 6.8.72 CPUTIN Temperature Sensor Over-temperature ...
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CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 1) Register Location: Power on Default Value: Attribute: Size: 7 Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 6.8.74 AUXTIN Temperature Sensor Temperature (High ...
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AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2) Register Location: 51h Attribute: Read Only Size: 8 bits 7 Bit 7: Temperature <0> of AUXTIN sensor, which is low byte, means 0.5 Bit 6-0: Reserved. 6.8.76 ...
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AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2) Register Location: Power on Default Value Attribute: Size Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 6.8.78 ...
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Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 6.8.80 AUXTIN Temperature Sensor Over-temperature(Low Byte) Register - Index 56h (Bank 2) Register Location: Power on Default Value: Attribute: Size: 7 Bit 7: Over-temperature ...
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Bit 7-6: Reserved. Bit 5: A one indicates the fan count limit of AUXFANIN1 has been exceeded . Bit 4: A one indicates the fan count limit of CPUFANIN1 has been exceeded . Bit 3: A one indicates a High ...
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Reserved Register - Index 52h (Bank 4) 6.8.84 BEEP Control Register 3 - Index 53h (Bank 4) Register Location: Power on Default Value: Attribute: Size Bit 7-6: Reserved. Bit 5: User define BEEP output function. Write 1, ...
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CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4) Register Location: Power on Default Value: Attribute: Size Bit 7-0: CPUTIN temperature offset value. The value in this register will be added to the monitored value so ...
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Reserved Register - Index 57h-58h (Bank 4) 6.8.89 Real Time Hardware Status Register I - Index 59h (Bank 4) Register Location: Power on Default Value: Attribute: Size Bit 7: CPUFANIN0 status. Read 1, the fan speed count ...
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Bit 7: Smart Fan of CPUFANIN0 warning status. Read 1, the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFan Read 0, the temperature does not ...
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Bit 6: Reserved. Bit 5: VIN2 Voltage status. Read 1, the voltage of VIN2 is over/under the limit value. Read 0, the voltage of VIN21 is in the limit range. Bit 4: VIN3 Voltage status. Read 1, the voltage of ...
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Configuration Register 7.1 Chip (Global) Control Register CR 02h. (Software Reset; Write Only) BIT READ / WRITE 7~1 Reserved. Software RESET. 0 Write “1” Only CR 07h. (Logic Device; Default 00h) BIT READ / WRITE 7 ...
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CR 24h. (Global Option; Default 0100_0ss0b) BIT READ / WRITE 7 Reserved. CLKSEL => Input clock rate selection Reserved. Enable SYSFANOUT as Output Buffer (For H version only ...
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CR 26h. (Global Option; Default 0s000000b) BIT READ / WRITE SEL4FDD => HEFRAS => The corresponding power-on strapping pin is RTSA# (pin 51). LOCKREG ...
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CR 27h. (Reserved) CR 28h. (Global Option; Default 50h) BIT READ / WRITE 7 Reserved. Flash ROM size select = 6 Select to enable/disable decoding of BIOS ROM range 000E ...
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CR 2Ah pin select; Default 00h) BIT READ / WRITE Reserved. 7~6 Serial flash interface configuration register.(VBAT Note: The bit will be ignored while CR24 bit-1 is low. Serial ...
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Continued. BIT READ / WRITE EN_PWRDN. (VBAT PIN78~85 function select 1~0 CR 2Dh. (GPIO5 and power control signals multi-function selection; default 21h) (VSB Power) BIT READ / WRITE PIN67 ...
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Continued. BIT READ / WRITE PIN75 Select (reset by RSMRST PIN77 Select (reset by RSMRST 2Eh. (Default 00h) BIT READ / WRITE 7~0 ...
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CR 74h. (Default 02h) BIT READ / WRITE 7~3 Reserved. These bits select DRQ resource for FDC. 2 000: DMA0. 1xx: No DMA active. CR F0h. (Default 8Eh) BIT READ / WRITE This bit controls the internal ...
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Continued. BIT READ / WRITE DISFDDWR => Enable FDD write. 1: Disable FDD write (forces pins WE, WD stay high). SWWP => 0: Normal, use WP to determine whether the FDD is write protected or ...
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TABLE A DRIVE RATE TABLE SELECT DRTS1 DRTS0 TABLE B DTYPE0 DTYPE1 DRVDEN0 (PIN W83627EHF/EF, W83627EHG/EG DATA RATE SELECTED DATA RATE DRATE1 DRATE0 MFM 1 ...
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Logical Device 1 (Parallel Port) CR 30h. (Default 01h) BIT READ / WRITE 7~1 Reserved. 0: Logical device is inactive Activate the logical device. CR 60h, 61h. (Default 03h, 78h) BIT READ / WRITE ...
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Logical Device 2 (UART A) CR 30h. (Default 01h) BIT READ / WRITE 7~1 Reserved. 0: Logical device is inactive Activate the logical device. CR 60h, 61h. (Default 03h, F8h) BIT READ / WRITE ...
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Logical Device 3 (UART B) CR 30h. (Default 01h) BIT READ / WRITE 7~1 Reserved. 0: Logical device is inactive Activate the logical device. CR 60h, 61h. (Default 02h, F8h) BIT READ / WRITE ...
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CR F1h. (Default 00h) BIT READ / WRITE Reserved. IRLOCSEL => IR I/O pins’ location selection Through SINB / SOUTB. 1: Through IRRX / IRTX. 5 IRMODE => ...
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Logical Device 5 (Keyboard Controller) CR 30h. (Default 01h) BIT READ / WRITE 7~1 Reserved. 0: Logical device is inactive Activate the logical device. CR 60h, 61h. (Default 00h,60h) BIT READ / WRITE These ...
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Continued. BIT READ / WRITE 0: Port 92 disable Port 92 enable. 0: Gate A20 software control Gate A20 hardware speed up. 0: KBRST software control ...
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CR 62h, 63h. (Default 03h, 30h) BIT READ / WRITE These two registers select MIDI Port base address <100h : FFEh> 7 bytes boundary. CR 70h. (Default 09h) BIT READ / WRITE 7~4 Reserved. 3~0 ...
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CR F3h. (GPIO1 I/O register; Default 00h) BIT READ / WRITE 0: GPIO17 GPIO17 0: GPIO16 GPIO16 0: GPIO15 GPIO15 0: GPIO14 ...
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CR F7h. (Game Port PAD control register; Default 00h) BIT READ / WRITE 7~1 Reserved. Joystick Power Down Joystick Power Down Disable. 1: Joystick Power Down Enable. 7.9 Logical Device 8 (WDTO# & PLED) CR ...
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CR F6h. (WDTO# counter register; Default 00h) BIT READ / WRITE Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. If the ...
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CR E0h. (GPIO5 I/O register; Default FFh) BIT READ / WRITE GPIO5 I/O register 7 The respective GPIO5 PIN is programmed as an Output port 1: The respective GPIO5 PIN is programmed as an Input port. ...
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CR E5h. (GPIO2 Inversion register; Default 00h) BIT READ / WRITE GPIO2 Inversion register 0: The respective bit and the port value are the same. 7 The respective bit and the port value are inverted. (Both ...
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CR F4h. (GPIO4 I/O register; Default FFh) BIT READ / WRITE GPIO4 I/O register 7 The respective GPIO4 PIN is programmed as an Output port 1: The respective GPIO4 PIN is programmed as an Input port. ...
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Logical Device A (ACPI) (CR30, CR70 are VCC powered; CRE0~F7 are VRTC powered) CR 30h. (Default 00h) BIT READ / WRITE 7~1 Reserved. 0: Logical device is inactive Activate the logical device. CR ...
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Continued. BIT READ / WRITE 3 Reserved. Keyboard / Mouse swap enable Normal mode. 1: Keyboard / Mouse ports are swapped. MSXKEY => 3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1 ...
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Continued. BIT READ / WRITE Thermal shutdown status. Read Only thermal shutdown event issued. Read-Clear 1: The thermal shutdown event issued. PSIN_STS Read Only PSIN event issued. Read-Clear 1: The PSIN event issued. MSWAKEUP_STS ...
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CR E5h. (Reserved) BIT READ / WRITE 7~0 Reserved. CR E6h. (Default 1Ch) BIT READ / WRITE ENMDAT => 3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1 define the combinations of the mouse wake-up events. Please ...
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CR E7h. (Default 00h) BIT READ / WRITE ENKD3 => Enable the third set of keyboard wake-up key combination. Its values are accessed through keyboard wake-up index register (CRE1) and keyboard wake-up data register (CRE2) at ...
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CR E8h. (Reserved) CR F2h. (Default 7Ch) (VSB power) BIT READ / WRITE 7 Reserved. Enable RSTOUT4# function Disable RSTOUT4#. 1: Enable RSTOUT4#. Enable RSTOUT3# function Disable RSTOUT3#. 1: Enable ...
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CR F4h. (Default 00h) BIT READ / WRITE 7~4 Reserved. PME status of the HM IRQ event W-Clear Write 1 to clear this status. PME status of the WDTO# event W-Clear Write 1 to ...
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Logical Device B (Hardware Monitor, for W83627EHF/EHG only) CR 30h. (Default 00h) BIT READ / WRITE 7~1 Reserved. 0: Logical device is inactive Activate the logical device. CR 60h, 61h. (Default 00h, 00h) BIT ...
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SPECIFICATIONS 8.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage (3.3V) Input Voltage RTC Battery Voltage V BAT Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability ...
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DC CHARACTERISTICS, continued. PARAMETER SYM. I/O - TTL level bi-directional pin with 24mA source-sink capability 24t Input Low Voltage V Input High Voltage V Output Low Voltage V Output High Voltage V Input High Leakage I Input Low Leakage I ...
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DC CHARACTERISTICS, continued. PARAMETER SYM. Input High Leakage I Input Low Leakage I I/O – 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability 24tsp3 Input Low Threshold V Voltage Input High Threshold V Voltage Hystersis V Output Low ...
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DC CHARACTERISTICS, continued. PARAMETER SYM. Input Low Leakage I/OD - TTL level Schmitt-trigger bi-directional pin and open drain output with 24mA sink 24ts capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis V Output Low Voltage V Input High ...
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DC CHARACTERISTICS, continued. PARAMETER SYM. I/OD - CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and 12 csd open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input ...
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DC CHARACTERISTICS, continued. PARAMETER SYM Output pin with 24mA source-sink capability 24 Output Low Voltage V Output High Voltage 3.3V output pin with 12mA source-sink capability 12p3 Output Low Voltage 3.3V output ...
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DC CHARACTERISTICS, continued. PARAMETER SYM TTL level input pin with internal pull up resistor tu Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage IN - TTL level Schmitt-trigger input pin ts Input Low Threshold ...
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DC CHARACTERISTICS, continued. PARAMETER SYM CMOS level Schmitt-trigger input pin cs Input Low Threshold Voltage Hystersis V Input High Leakage Input Low Leakage IN - CMOS level Schmitt-trigger input pin with internal pull up resistor csu Input Low ...
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AC CHARACTERISTICS 8.3.1 Power On / Off Timing PSON# SUSB# (Intel Chipset) SUSB# (SiS/VIA/Nvidia Chipset) PSOUT# T1 PSIN VSB Typical Timing (Sec) W83627EHF/EF, W83627EHG/ 61m 131 - T4 S5 ...
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AC Power Failure Resume Timing 1. CRE4 bit7 = “0” and CRE4 bit[6:5] are selected to “OFF” state (“OFF” means always turn off or last state is off) VCC PSOUT# PSON# SUSB# RSMRST# VSB ACLOSS 2. CRE4 bit7 = ...
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CRE4 bit7 = “1” and CRE4 bit[6:5] are selected to “OFF” state (“OFF” means always turn off or last state is off) VCC PSOUT# PSON# SUSB# RSMRST# VSB ACLOSS 4. CRE4 bit7 = “1” and CRE4 bit[6:5] are selected ...
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What’s the definition of last state when AC power failure? 1) Last state is “ON” VCC is falling to 2.6V and SUSB# keeps VIH 2.0V VCC SUSB# 2) Last state is “OFF” VCC is falling to 2.6V and SUSB# ...
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CR E4h Power loss control bits => 00: System always turns off when come back from power loss state. 01: System always turns on when come back from power loss state. 6 10: System turns off / ...
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... HOW TO READ THE TOP MARKING inbond W83627EHF 330G9A282012345UB inbond W83627EF 330G9A282012345UB 1st line: Winbond logo 2nd line: the type number: W83627EHF/EF, W83627EHG/EG (Pb-free package) 3rd line: the tracking code 030A7C282012345UA 330: packages made in '03, week 30 G: assembly house ID; G means GR, A means ASE ... etc. ...
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PACKAGE SPECIFICATION (128-pin PQFP 102 103 128 See Detail F y Seating Plane W83627EHF/EF, W83627EHG/ Detail F ...
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Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other ...