ada4320-1 Analog Devices, Inc., ada4320-1 Datasheet - Page 12

• Manufacturer Part Number: ada4320-1
• Description: High Power, Low Distortion Upstream Catv Line Driver Ada4320-1
• Manufacturer: Analog Devices, Inc.

ADA4320-1
POWER SAVING FEATURES
The ADA4320-1 incorporates three distinct methods for
reducing power consumption that include the following:
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•
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The asynchronous TXEN pin is used to place the ADA4320-1
into between-burst mode. In this reduced current state, the
300 Ω differential output impedance is maintained. Applying
Logic 0 to the TXEN pin deactivates the amplifier, providing
up to 95% reduction in consumed power. For 5 V operation at
maximum gain and current level, supply current is typically
reduced from 260 mA to 12 mA. In this mode of operation,
between-burst noise is minimized and over 100 dB of input to
output isolation is achieved.
Additionally, the ADA4320-1 incorporates an asynchronous
SLEEP pin that can be used to further reduce supply current to
approximately 12 μA. Applying Logic 0 to the SLEEP pin places
the amplifier into sleep mode.
Entering/exiting sleep mode can result in a transient voltage at the
output of the amplifier. It is recommended to perform transitions
on the SLEEP pin with TXEN held low.
Additional power savings are possible by optimizing the output
stage current for different operating conditions. Typically, at
lower frequencies (5 MHz to 42 MHz), the full specified output
can be maintained in CL0 (see Figure 13 and Figure 16). For lower
input levels, the same is true, as shown in Figure 17 and Figure 20.
For per-channel output levels less than 65 dBmV (QPSK) and
50 dBmV (4× QAM64), the ADA4320-1 can maintain an ACPR
of better than −60 dBc (see Figure 18 and Figure 21) at Current
Level 0 (CL0). At higher gain settings, operating in CL0 reduces
current consumption by 30%, compared to operating in CL3.
As an example, operating in CL0, the ADA4320-1 can drive a
single QPSK channel at 61 dBmV, at maximum gain, maintaining
a worst-case ACPR of −66 dBc. It does this while drawing only
180 mA from a 5 V supply.
INPUT BIAS, IMPEDANCE, AND TERMINATION
The VIN+ and VIN− inputs have a dc bias level of V
therefore, the input signal should be ac-coupled as seen in the
typical application circuit (see Figure 24). The differential input
impedance of the ADA4320-1 is approximately 640 Ω, and the
single-ended input is 320 Ω. The ADA4320-1 exhibits optimum
performance when driven with a balanced (differential) signal.
Transmit disable for between-burst periods
Sleep (shutdown) mode
Output stage current scaling
CC
/2;
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OUTPUT BIAS, IMPEDANCE, AND TERMINATION
The output stage of the ADA4320-1 requires a bias of 5 V.
The 5 V power supply should be applied to the center tap of
the output transformer through a 100 nH series inductor. This
supply should also be decoupled with a 0.1 μF capacitor, as shown
in Figure 24.
The output impedance of the ADA4320-1 is 300 Ω differential,
regardless of whether the amplifier is in transmit enable, transmit
disable, or sleep mode. This, when combined with a 4:1 impedance
transformer, provides a 75 Ω output match and eliminates the
need for external back termination resistors. If the output signal
is being evaluated using standard 50 Ω test equipment, a minimum
loss 75 Ω to 50 Ω pad should be used to provide the test circuit
with the proper impedance match.
POWER SUPPLY
The 5 V supply should be delivered to each of the VCC pins via
a low impedance power bus. The power bus should be decoupled
with a 10 μF tantalum capacitor located close to the ADA4320-1.
Additionally, the VCC pins require decoupling to ground with
ceramic chip capacitors located close to the pins. Pin 24 (COMP),
should also be decoupled. The ideal printed circuit board (PCB)
has a low impedance ground plane covering all unused portions
of the board, except in areas of the board where input and output
traces are in close proximity to the ADA4320-1 and the output
transformer. All device GND pins, as well as the exposed pad,
must contact the PCB ground plane to ensure proper grounding
of all internal nodes.
SIGNAL INTEGRITY LAYOUT CONSIDERATIONS
Careful attention to PCB layout details can prevent problems
due to board parasitics. Proper RF design techniques are highly
recommended. All balanced input/output traces should be kept
as short as possible. This minimizes parasitic capacitance and
inductance, which is most critical between the outputs of the
ADA4320-1 and the 4:1 output transformer. It is also recommended
that all balanced signal paths be symmetrical in length and width.
Additionally, input and output traces should be adequately spaced
to minimize coupling (crosstalk) through the board. Following
these guidelines optimizes the overall performance of the
ADA4320-1 in all applications.
INITIAL POWER-UP
When supply voltage is applied to the ADA4320-1, the gain of
the amplifier is initially undetermined. During amplifier power-
up, the TXEN pin should be held low (Logic 0) to prevent forward
signal transmission. Gain must then be set to the desired level,
followed by TXEN driven high. Forward signal transmission is
enabled at the resultant gain level.