at49bv320ct ATMEL Corporation, at49bv320ct Datasheet - Page 3

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at49bv320ct

Manufacturer Part Number
at49bv320ct
Description
32-megabit 2m X 16 3-volt Only Flash Memory
Manufacturer
ATMEL Corporation
Datasheet

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3. Block Diagram
4. Device Operation
4.1
4.2
3372F–FLASH–4/05
A0 - A20
Read
Command Sequences
Y-DECODER
X-DECODER
ADDRESS
BUFFER
LATCH
INPUT
When the AT49BV320C(T) is in the read mode, with CE and OE low and WE high, the data
stored at the memory location determined by the address pins are asserted on the outputs. The
outputs are put in the high impedance state whenever CE or OE is high. This dual-line control
gives designers flexibility in preventing bus contention.
When the device is first powered on, it will be in the read mode. In order to perform other device
functions, a series of command sequences are entered into the device. The command
sequences are shown in the
inputs for the command codes). The command sequences are written by applying a low pulse
on the WE or CE input with CE or WE low (respectively) and OE high. The address and data are
latched by the first rising edge of CE or WE. Standard microprocessor write timings are used.
OUTPUT
BUFFER
COMPARATOR
MEMORY
IDENTIFIER
I/O0 - I/O15
REGISTER
REGISTER
Y-GATING
STATUS
MAIN
DATA
“Command Definition Table” on page 15
BUFFER
INPUT
WRITE STATE
COMMAND
REGISTER
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
AT49BV320C(T)
(I/O8 - I/O15 are don’t care
CE
WE
OE
RESET
WP
VPP
VCC
GND
3

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