at49bv320ct ATMEL Corporation, at49bv320ct Datasheet - Page 5

• Manufacturer Part Number: at49bv320ct
• Description: 32-megabit 2m X 16 3-volt Only Flash Memory
• Manufacturer: ATMEL Corporation

4.7
Table 4-1.
Note:
3372F–FLASH–4/05
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
SR4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
SR1 = SECTOR LOCK STATUS
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
SR0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
WSMS
7
Read Status Register
1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
Status Register Bit Definition
ESS
6
The status register indicates the status of device operations and the success/failure of that oper-
ation. The Read Status Register command causes subsequent reads to output data from the
status register until another command is issued. To return to reading from the memory, issue a
Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE or OE must be toggled with each subsequent status read,
or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing the
preferred operation (see
ES
5
Table
PS
4
4-1).
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
When this bit is set to “1”, WSM has attempted but failed to
program a word
The V
level. The WSM interrogates V
Erase command sequences have been entered and informs the
system if V
before the operation is verified by the WSM.
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
This bit is reserved for future use and should be masked out
when polling the status register.
VPPS
PP
3
status bit does not provide continuous indication of VPP
PP
has not been switched on. The V
PSS
2
Notes
PP
AT49BV320C(T)
level only after the Program or
SLS
1
PP
is also checked
R
0
5