at49bv320ct ATMEL Corporation, at49bv320ct Datasheet - Page 4

• Manufacturer Part Number: at49bv320ct
• Description: 32-megabit 2m X 16 3-volt Only Flash Memory
• Manufacturer: ATMEL Corporation

4.3
4.4
4.4.1
4.5
4.6
4
Reset
Erasure
Word Programming
VPP Pin
AT49BV320C(T)
Sector Erase
The address locations used in the command sequences are not affected by entering the com-
mand sequences.
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET input halts the
present device operation and puts the outputs of the device in a high impedance state. When a
high level is reasserted on the RESET pin, the device returns to the read mode, depending upon
the state of the control inputs.
Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a
logical “1”. The individual sectors can be erased by using the Sector Erase command.
The device is organized into 71 sectors (SA0 - SA70) that can be individually erased. The Sector
Erase command is a two-bus cycle operation. The sector address and the D0H Data Input com-
mand are latched on the rising edge of WE. The sector erase starts after the rising edge of WE
of the second cycle provided the given sector has not been protected. The erase operation is
internally controlled; it will automatically time to completion. The maximum time to erase a sector
is t
ing immediately.
Once a memory sector is erased, it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the Internal Device command register and is a two-bus cycle
operation. The device will automatically generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If a
hardware reset happens during programming, the data at the location being programmed will be
corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase opera-
tions can convert “0”s to “1”s. Programming is completed after the specified t
program status bit is a “1”, the device was not able to verify that the program operation was per-
formed successfully. The status register indicates the programming status. While the program
sequence executes, status bit I/O7 is “0”. While programming, the only valid commands are
Read Status Register, Program Suspend and Program Resume.
The circuitry of the AT49BV320C(T) is designed so that the device cannot be programmed or
erased if the V
erase operations can be performed. The VPP pin cannot be left floating.
SEC
. An attempt to erase a sector that has been protected will result in the operation terminat-
PP
voltage is less that 0.4V. When V
PP
is at 1.5V or above, normal program and
BP
cycle time. If the
3372F–FLASH–4/05