w942516ah Winbond Electronics Corp America, w942516ah Datasheet
w942516ah
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w942516ah Summary of contents
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... W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words m process technology, W942516AH delivers a data bandwidth 286M words per second (-7). To fully comply with the personal computer industrial standard, W942516AH is sorted into three speed grades: -7, -75 and -8 ...
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... BS0 26 BS1 W942516AH DQ15 DQ14 62 DQ13 DQ12 59 DQ11 DQ10 56 DQ9 DQ8 ...
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... REF Voltage Ground Ground for logic circuit inside DDR SDRAM. Separated power from V noise. Separated ground from V buffer noise W942516AH Description A12. A8. (A10 is used for Auto Precharge) ) define the command being CS , used for output buffer, to improve DD , used for output buffer, to improve SS Publication Release Date: May 2001 Revision 0 ...
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... BANK #0 SENSE AMPLIFIER PREFETCH REGISTER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 8912 * 512 * W942516AH COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ0 DQ BUFFER DQ15 LDQS, UDQS LDM, UDM COLUMN DECODER CELL ARRAY ...
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... V -0.3 IL (DC -0.3 ICK (DC V 0.36 ID (DC 0.31 IH (AC) REF (AC) V 0.7 ID (AC Q/2 - 0.2 (AC Q/2 - 0.2 ISO (AC) DD Q+0.9V with a pulse width < W942516AH RATING UNIT -0 +0 -0 °C -55 ~ 150 °C 260 ° TYP. MAX. UNIT 2.5 2.7 V 2.5 VDD ...
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... Input Capacitance (except for CLK pins) Input Capacitance (CLK pins) DQ, DQS, DM capacitance NC pin capacitance Note: These parameters are periodically sampled and not 100% tested. = 25°C, V (DC Q/2, V (Peak to Peak) = 0.2V) A OUT DD OUT SYMBOL MIN CLK C I W942516AH DELTA MAX. (MAX.) 2.0 3.5 - 2.0 3.5 - 4.0 5.0 0.5 - 1.5 - UNIT ...
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... All Banks Idle min CK min; CKE > V min; One min; DQ, DM and min RFC = RCD OUT - 7 - W942516AH Max. UNIT -7 - 110 110 100 DD0 I 110 110 100 DD1 DD2P DD2F ...
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... Row f Row SYMBOL I I( Full Strength I OH (DC (DC (DC) Half Strength I OL (DC W942516AH READ ACT ACT AP AP Bank 3 Bank 2 Bank 0 Row q Col f Row MIN. MAX. UNITS - 0.76 - ...
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... CH -0.75 -0.75 0.9 1.1 0.9 0.4 0.6 0.4 0.5 0.5 0.5 0.5 1.75 1.75 0.35 0.35 0.35 0.35 0.2 0.2 0.2 0 0.25 0.25 0.4 0.4 0.75 1.25 0.75 -0.25 0.25 -0.25 0.9 0.9 0.9 0.9 2.2 2.2 -0.75 0.75 -0.75 -0.75 0.75 -0.75 0.5 1.5 0 W942516AH (NOTES: 10, 12) -75 -8 UNITS MAX. MIN. MAX 100000 50 100000 0.75 -0.8 0.8 0.75 -0.8 0.8 0.5 0.6 0.55 0.45 0. 0.55 0.45 0.55 min ) ( -1.0 HP 1.1 0.9 1 0.6 0.4 0.6 0.6 0 0.35 0.35 0 ...
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... SLEW Input signal minmum slew rate V Output timing measurement refernece voltage OTR V DDQ V (max) SWING CLK Vss t SLEW=V IHmin(AC) PARAMETER V (AC) IHmin VREF V (AC) ILmax ILmax(AC W942516AH VALUE UNIT NOTE V +0.31 V REF V -0.31 V REF 0.5xV V DDQ 0.5xV V DDQ 1 (AC 1.5 V 1.0 V/ns ...
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... V .Transition (rise and fall) of input signals have a fixed IH min(AC) IL max(AC) contains more than one decimal place, the result is rounded 7.5ns = 5.625ns is rounded up to 5.6ns.) ( CLK )}/ ICK V ISO(max W942516AH ICK ID(AC) Publication Release Date: May 2001 Revision 0.0 ...
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... CKE signal is input level one clock cycle before the commands are issued. n-1 3. These are state designated by the BS0,BS1 signals. 4. LDM, UDM (W942516AH) 5. Power Down Mode can not entry in the burst cycle. (4) CKE CKE DM BS0, ...
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... READ/READ Term burst, start read: Determine AP L BS,CA,A10 WRIT/WRIT Term burst, start read: Determine AP BS,RA ACT ILLEGAL L BS,A10 PRE/PREA Term burst. precharging X AREF/SELF ILLEGAL L Op-Code MRS/EMRS ILLEGAL - 13 - W942516AH Action Notes 6.7 Publication Release Date: May 2001 Revision 0 ...
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... X NOP L X BST H BS,CA,A10 READ/READA L BS,CA,A10 WRIT/WRITA H BS,RA ACT L BS,A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 14 - W942516AH Action Notes Continue burst to end Continue burst to end ILLEGAL 3 ILLEGAL ILLEGAL 3 ILLEGAL 3 ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL 3 ILLEGAL 3 ILLEGAL 3 ILLEGAL ...
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... X X AREF/SELF/MRS/EMRS X X DSL X NOP L X BST X X READ/WRIT X X ACT/PRE/PREA/AREF W942516AH Action Notes Nop->dle after t RC Nop->Idle after t RC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Enter precharge after t WR Nop->Enter precharge after t WR ILLEGAL ...
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... Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table - 16 - W942516AH Action Notes XSNR XSNR ...
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... AREF IDLE PD PDEX ACT PDEX PD ROW ACTIVE Read Write Read Read A Write A Read A PRE PRE PRE PRE CHARGE PRE - 17 - W942516AH SELF REFRESH AUTO REFRESH POWER DOWN BST Read Read Read A Read A Automatic Sequence Command Sequence Publication Release Date: May 2001 Revision 0.0 ...
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... The write command performs a Write operation to the bank designated by BS. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation. 2-5 Write with Auto Precharge command 0.2V and REF - 18 - W942516AH ...
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... DLL. Refer to the table for specific codes. 2-10 No-Operation command ( RAS =”H”, CAS =”H”, WE =”H”) The No-Operation command simply performs no operation (same command as Device Deselect). 2-11 Burst Read stop command CK - (BL/ RAS(min W942516AH Publication Release Date: May 2001 Revision 0.0 ...
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... Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation. from the end of the Auto Refresh command. When the Auto Refresh from the Bank Activate command, the data is read out sequentially W942516AH ...
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... Self Refresh mode. In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8us and the last distributed from the bank activate command. The input data is latched RCD . Therefore, each bank must be precharged RAS (max) . RFC - 21 - W942516AH WR Publication Release Date: May 2001 Revision 0.0 to ...
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... Power Down Mode enter asserting CKE “low” while the device is not running a burst cycle. Taking cke :high” can exit this mode. When CKE goes high operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode W942516AH ...
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... A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both addressing Mode support burst length 2, 4, and 8 words Burst Length Reserved words words words Reserved A3 Addressing mode 0 Sequential 0 Interleave - 23 - W942516AH Publication Release Date: May 2001 Revision 0.0 ...
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... Data BURST LENGTH 2 words (address bits is A0) No carried from words (address bit A0, A1) Not carried from words(address bits A2, A1 and A0) Not carried from ACCESS ADDRESS - 24 - W942516AH BURST LENGTH 2 words 4 words 8 words ...
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... Reserved Reserved Reserved 2 Reserved BS1 BS0 A12- Regular MRS cycle 0 1 Extended MRS cycle 1 x Reserved A0 DLL 0 Enable 1 Disable A1 Output driver 0 Full strength 1 Half strength - 25 - W942516AH Publication Release Date: May 2001 Revision 0.0 ...
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... PACKAGE DIMENSION 66L TSOP - 400 mil - 26 - W942516AH ...