nanda9w3m1 Numonyx, nanda9w3m1 Datasheet - Page 16

• Manufacturer Part Number: nanda9w3m1
• Description: 256/512-mbit Or 1-gbit X8/x16, 1.8/2.6 V, 528-byte Page Nand Flash And 256/512-mbit X16/x32, 1.8 V Lpsdram, Mcp Or Pop
• Manufacturer: Numonyx

Signals description
2
2.1
2.2
2.3
2.4
2.5
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Signals description
Figure 1
the signals connected to NANDxxxxMx devices. This section provides further information on
the signals.
For additional details on the signals, refer to the NAND flash memory and the LPSDRAM
datasheets.
Flash memory inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used by the flash memory to input the selected address, output the
data during a read operation, or input a command or data during a write operation. The
inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the
device is deselected or the outputs are disabled.
Flash memory inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 NAND flash devices. They are used to output
the data during a read operation or input data during a write operation. Command and
address inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
Flash memory Address Latch Enable (AL)
The Address Latch Enable, AL, activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
Flash memory Command Latch Enable (CL)
The Command Latch Enable, CL, activates the latching of the command inputs in the
command interface. When CL is High, the inputs are latched on the rising edge of Write
Enable.
Flash memory Chip Enable (E
The Chip Enable input, E
read circuitry. When Chip Enable is Low, V
If Chip Enable goes High (V
does not go into standby mode.
and
Figure
2, in conjunction with
F
, activates the memory control logic, input buffers, decoders, and
IH
) while the device is busy, the device remains selected and
Table 4
IL
, the device is selected.
F
)
and
Table
5, provide a brief overview of
NANDxxxxMx