CD4023BCM Fairchild Semiconductor, CD4023BCM Datasheet

Gates (AND / NAND / OR / NOR) Trp 3-Inp NAND Gate

CD4023BCM

Manufacturer Part Number
CD4023BCM
Description
Gates (AND / NAND / OR / NOR) Trp 3-Inp NAND Gate
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of CD4023BCM

Product
NAND
Logic Family
CD4000
Number Of Gates
3
Number Of Lines (input / Output)
3 / 1
High Level Output Current
- 4.2 mA
Low Level Output Current
4.2 mA
Propagation Delay Time
250 ns
Supply Voltage (max)
15 V
Supply Voltage (min)
5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOIC-14 Narrow
Minimum Operating Temperature
- 55 C
Lead Free Status / Rohs Status
No
© 2000 Fairchild Semiconductor Corporation
CD4023BCM
CD4023BCS
CD4023BCN
CD4023BC
Buffered Triple 3-Input NAND Gate
General Description
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-
channel enhancement mode transistors. They have equal
source and sink current capabilities and conform to stan-
dard B series output drive. The devices also have buffered
outputs which improve transfer characteristics by providing
very high gain. All inputs are protected against static dis-
charge with diodes to V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code.
Connection Diagram
Order Number
Package Number
DD
Top View
M14A
M14D
N14A
and V
SS
.
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS005956
Features
Block Diagram
1
*All Inputs Protected by Standard CMOS Input Protection Circuit.
/
3
Device Shown
Wide supply voltage range:
High noise immunity: 0.45 V
Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74LS
5V–10V–15V parametric ratings
Symmetrical output characteristics
Maximum input leakage 1 A at 15V over full
temperature range
Package Description
October 1987
Revised August 2000
DD
3.0V to 15V
(typ)
www.fairchildsemi.com

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CD4023BCM Summary of contents

Page 1

... V and Ordering Code: Order Number Package Number CD4023BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow CD4023BCS M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4023BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “ ...

Page 2

Absolute Maximum Ratings (Note 2) DC Supply Voltage ( Input Voltage ( Storage Temp. Range ( Power Dissipation ( Dual-In-Line Small Outline Lead Temperature ( ...

Page 3

AC Electrical Characteristics pF 200k, unless otherwise specified Symbol Parameter t Propagation Delay, HIGH-to-LOW Level PHL t Propagation Delay, LOW-to-HIGH Level PLH t , Transition Time THL t TLH C Average ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow www.fairchildsemi.com Package Number M14A 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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