s-24cs16a Seiko Instruments Inc., s-24cs16a Datasheet - Page 16

• Manufacturer Part Number: s-24cs16a
• Description: 2-wire Cmos Serial E2prom
• Manufacturer: Seiko Instruments Inc.

16
2-WIRE CMOS SERIAL E
S-24CS16A
7. Read
7. 1 Current Address Read
Either in writing or in reading the E
The memory address is maintained as long as the power voltage is higher than the current address hold voltage
V
The master device can read the data at the memory address of the current address pointer without assigning the
word address as a result, when it recognizes the position of the address pointer in the E
“Current Address Read”.
In the following the address counter in the E
When the E
start condition, it responds with an acknowledge. However, the page address (P2, P1 and P0) become invalid and
the memory address of the current address pointer becomes valid.
Next an 8-bit data at the address “n” is sent from the E
is incremented at the falling edge of the SCL clock for the 8th bit data, and the content of the address counter
becomes n + 1.
The master device outputs stop condition not an acknowledge, the reading of E
Attention should be paid to the following point on the recognition of the address pointer in the E
In the read operation the memory address counter in the E
edge of the SCL clock for the 8th bit of the output data. In the write operation, on the other hand, the upper bits of
the memory address (the upper bits of the word address and page address)
incremented at the falling edge of the SCL clock for the 8th bit of the received data.
*1. The upper 4 bits of the word address and the page address P2, P1 and P0.
AH
.
SDA LINE
2
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a
S
A
R
T
T
M
S
B
1
2
PROM
0
ADDRESS
1
2
DEVICE
PROM holds the last accessed memory address, internally incremented by one.
Figure 17 Current Address Read
0
P2 P1 P0
Seiko Instruments Inc.
2
PROM is assumed to be “n”.
S
B
L
W
R
1
/
R
E
A
D
2
PROM synchronous to the SCL clock. The address counter
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
2
PROM is automatically incremented at every falling
Master Device
NO ACK from
DATA
2
PROM is ended.
*1
are left unchanged and are not
ADR INC
2
PROM. This is called
2
PROM.
S
O
P
T
Rev.5.1
00