lm5035bsqx National Semiconductor Corporation, lm5035bsqx Datasheet - Page 19

• Manufacturer Part Number: lm5035bsqx
• Description: Pwm Controller With Integrated Half-bridge And Syncfet Drivers
• Manufacturer: National Semiconductor Corporation

on of the high-side MOSFET. The capacitor should be large
enough to supply the MOSFET gate charge (Qg) without dis-
charging to the point where the drop in gate voltage affects
the MOSFET R
ommended.
The diode (D
low-side MOSFET is conducting should be capable of with-
standing the full converter input voltage range. When the
high-side MOSFET is conducting, the reverse voltage at the
diode is approximately the same as the MOSFET drain volt-
age because the high-side driver is boosted up to the con-
verter input voltage by the HS pin, and the high side MOSFET
gate is driven to the HS voltage plus VCC. Since the anode
of D
the diode is equal to the input voltage minus the VCC voltage.
D
tions, so a low current ultra-fast recovery diode is recom-
mended to limit the loss due to diode junction capacitance.
Schottky diodes are also a viable option, particularly for lower
input voltage applications, but attention must be paid to leak-
age currents at high temperatures.
The internal gate drivers need a very low impedance path to
the respective decoupling capacitors; the VCC cap for the LO
driver and C
should be as short as possible to reduce inductance and as
wide as possible to reduce resistance. The loop area, defined
by the gate connection and its respective return path, should
be minimized.
The high-side gate driver can also be used with HS connected
to PGND for applications other than a half bridge converter
(e.g. Push-Pull). The HB pin is then connected to VCC, or any
supply greater than the high-side driver undervoltage lockout
(approximately 6.5V). In addition, the high-side driver can be
configured for high voltage offline applications where the
high-side MOSFET gate is driven via a gate drive transformer.
PROGRAMMABLE DELAY (DLY)
The R
SR2 signals and the HO and LO driver outputs. Figure 5
shows the relationship between these outputs. The DLY pin
is nominally set at 2.5V and the current is sensed through
R
deadtime before the HO and LO pulse (T1) and after the HO
and LO pulse (T2). Typically R
100kΩ. The deadtime periods can be calculated using the
following formulae:
This may cause lower than optimal system efficiency if the
delays through the SR signal transformer network, the sec-
ondary gate drivers and the SR MOSFETs are greater than
the delay to turn on the HO or LO MOSFETs. Should an SR
MOSFET remain on while the opposing primary MOSFET is
BOOST
DLY
BOOST
to ground. This current is used to adjust the amount of
DLY
average current is less than 20mA in most applica-
resistor programs the delays between the SR1 and
is connected to VCC, the reverse potential across
BOOST
BOOST
DS(ON)
T2 = .0007 x R
T1 = .003 x R
) that charges C
for the HO driver. These connections
. A value ten to twenty times Qg is rec-
DLY
DLY
DLY
+ 10.01 ns
BOOST
is in the range of 10kΩ to
+ 4.6 ns
from VCC when the
19
supplying power through the power transformer, the sec-
ondary winding will experience a momentary short circuit,
causing a significant power loss to occur.
When choosing the R
lays and component tolerances should be considered to as-
sure that there is never a time where both SR MOSFETs are
enabled AND one of the primary side MOSFETs is enabled.
The time period T1 should be set so that the SR MOSFET has
turned off before the primary MOSFET is enabled. Converse-
ly, T1 and T2 should be kept as low as tolerances allow to
optimize efficiency. The SR body diode conducts during the
time between the SR MOSFET turns off and the power trans-
former begins supplying energy. Power losses increase when
this happens since the body diode voltage drop is many times
higher than the MOSFET channel voltage drop. The interval
of body diode conduction can be observed with an oscillo-
scope as a negative 0.7V to 1.5V pulse at the SR MOSFET
drain.
UVLO AND OVP VOLTAGE DIVIDER SELECTION FOR R1,
R2, AND R3
Two dedicated comparators connected to the UVLO and OVP
pins are used to detect under-voltage and over-voltage con-
ditions. The threshold value of these comparators, V
V
grammed independently with two voltage dividers from VIN to
AGND as shown in Figure 10 and Figure 11, or with a three-
resistor divider as shown in Figure 12. Independent UVLO
and OVP pins provide greater flexibility for the user to select
the operational voltage range of the system. Hysteresis is ac-
complished by 23 µA current sources (I
are switched on or off into the sense pin resistor dividers as
the comparators change state.
When the UVLO pin voltage is below 0.4V, the controller is in
a low current shutdown mode. For a UVLO pin voltage greater
than 0.4V but less than 1.25V the controller is in standby
mode. Once the UVLO pin voltage is greater than 1.25V, the
controller is fully enabled. Two external resistors can be used
to program the minimum operational voltage for the power
converter as shown in Figure 10. When the UVLO pin voltage
falls below the 1.25V threshold, an internal 23 µA current sink
is enabled to lower the voltage at the UVLO pin, thus providing
threshold hysteresis. Resistance values for R1 and R2 can
be determined from the following equations.
where V
desired UVLO hysteresis at V
For example, if the LM5035B is to be enabled when V
reaches 34V, and disabled when VPWR is decreased to 32V,
R1 should be 87 kΩ, and R2 should be 3.54kΩ. The voltage
at the UVLO pin should not exceed 7V at any time. Be sure
to check both the power and voltage rating (0603 resistors
can be rated as low as 50V) for the selected R1 resistor.
OVP
, is 1.25V (typical). The two functions can be pro-
PWR
is the desired turn-on voltage and V
DLY
value, worst case propagation de-
PWR
.
UVLO
and I
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OVP
HYS
UVLO
), which
is the
PWR
and