tmp89fm82t TOSHIBA Semiconductor CORPORATION, tmp89fm82t Datasheet - Page 211

• Manufacturer Part Number: tmp89fm82t
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA005
14.4.5
14.4.5.1
14.4.5.2
14.4.5.3
longer period than an 8-bit timer.
In the 16-bit timer mode, TC00 and TC01 are cascaded to form a 16-bit timer counter, which can measure a
16-bit timer mode
of TC00 are ignored and those of TC01 are effective in the 16-bit mode.
"0". Select the source clock at T01MOD<TCK1>.
T01REG. Set the lower 8 bits of the 16-bit value at T00REG and the higher 8 bits at T01REG. (Hereinafter,
the 16-bit value specified by the combined setting of T01REG and T00REG is indicated as T01+00REG.)
The timer register settings are reflected on the double buffer or T01+00REG when a write instruction is
executed on T01REG. Be sure to execute the write instructions on T00REG and T01REG in this order. (When
data is written to the high-order register, the set values of the low-order and high-order registers become
effective at the same time.)
becomes invalid. Be sure to complete the required mode settings before starting the timer. (Make settings
when T001CR<T00RUN> and <T01RUN> are "0".)
source clock. When a match between the up counter value and the T00+01REG set value is detected, an
INTTC01 interrupt request is generated and the up counter is cleared to "0x0000". After being cleared, the
up counter restarts counting. Setting T001CR<T01RUN> to "0" during the timer operation makes the up
counter stop counting and be cleared to "0x0000".
by setting T01MOD<DBE1> to "0" or enabled by setting T01MOD<DBE1> to "1".
Setting T001CR<TCAS> to "1" connects TC00 and TC01 and activates the 16-bit mode. All the settings
The 16-bit timer mode is activated by setting T01MOD<TCM1> to "00" or "01" and T01MOD<EIN1> to
Set the count value to be used for the match detection as a 16-bit value at the timer registers T00REG and
Set T01MOD<DBE1> to "1" to use the double buffer.
Setting T001CR<T01RUN> to "1" starts the operation. After the timer is started, writing to T01MOD
Setting T001CR<T01RUN> to "1" allows the 16-bit up counter to increment based on the selected internal
The double buffer can be used for T01+00REG by setting T01MOD<DBE1>. The double buffer is disabled
Setting
Operations
Double buffer
・ When the double buffer is enabled
・ When the double buffer is disabled
operation, the set value is first stored in the double buffer, and T01+00REG is not updated im-
mediately. T01+00REG compares the previous set value with the up counter value. When the
values are matched, an INTTC01 interrupt request is generated and the double buffer set value is
stored in T01+00REG. Subsequently, the match detection is executed using a new set value.
stopped, the set value is immediately stored in both the double buffer and T01+00REG.
operation, the set value is immediately stored in T01+00REG. Subsequently, the match detection
is executed using a new set value.
executed using a new set value after the up counter overflows. Therefore, the interrupt request
When write instructions are executed on T00REG and T01REG in this order during the timer
When write instructions are executed on T00REG and T01REG in this order while the timer is
When write instructions are executed on T00REG and T01REG in this order during the timer
If the value set to T01+00REG is smaller than the up counter value, the match detection is
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