tmp89fm82t TOSHIBA Semiconductor CORPORATION, tmp89fm82t Datasheet - Page 286

• Manufacturer Part Number: tmp89fm82t
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

17.5
SEI Transfer Formats
RA000
17.5.2
register while data transfer is in progress causes collision of writes. Therefore, wait until the SEF flag is set before
writing new data to the SEDR register.
Table 17-5 Transfer Format Details when CPHA = 1
Figure 17-3 shows a transfer format when CPHA = 1.
In master / slave mode, the SEF flag (SESR<SEF>) is set after the last shift cycle. Writing data to the SEDR
CPHA = 1 format
SECLK Cycle
SECLK
(CPOL = 0)
SECLK
(CPOL = 1)
MISO
SS
SEF
MOSI
・ Master mode
・ Slave mode
CPOL=0
CPOL=1
MOSI pin at the first edge of the shift clock. Use BOS (SECR<BOS>) to select whether the data should
be shifted out beginning with the MSB or LSB.
gardless of whether the SS pin is “L” or “H”.
Transfer is initiated by writing new data to the SEDR register. The new data changes state on the
Unlike in the case of CPHA = 0 format, data can be written to the SEDR (SEI Data Register) re-
Figure 17-3 Transfer Format When CPHA = 1
SECLK Level when Not
Communicating (IDLE)
“H” level
“L” level
1
2
Rising edge of transfer clock
Falling edge of transfer clock
3
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4
Data Shift
5
6
Falling edge of transfer clock
Rising edge of transfer clock
7
8
Data Sampling
Internal
Shift clock
TMP89FM82T