tmp89fm82t TOSHIBA Semiconductor CORPORATION, tmp89fm82t Datasheet - Page 258

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tmp89fm82t

Manufacturer Part Number
tmp89fm82t
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
16.2
Control
RA001
Serial interface control register
(0x001F)
SIO0CR
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: After the operation is started by writing "1" to SIOS, writing to SIOEDG, SIOCKS and SIODIR is invalid until
Note 3: After the operation is started by writing "1" to SIOS, no values other than"00" can be written to SIOM until SIOF becomes
Note 4: SIOS remains at "0", if "1" is written to SIOS when SIOM is "00" (operation stop).
Note 5: When SIO is used in SLOW1/2 or SLEEP1 mode, be sure to set SIOCKS to "110". If SIOCKS is set to any other value,
Note 6: When STOP, IDLE0 or SLEEP0 mode is activated, SIOM is automatically cleared to "00" and SIO stops the operation.
SIOEDG
SIOCKS
SIODIR
Read/Write
Bit Symbol
After reset
SIO0SR<SIOF> becomes "0". (SIOEDG, SIOCKS and SIODIR can be changed at the same time as changing SIOS from
"0" to "1".)
"0" (if a value from "01" to "11" is written to SIOM, it is ignored). The transfer mode cannot be changed during the operation.
SIO will not operate. When SIO is used in SLOW1/2 or SLEEP1 mode, execute communications with SIOCKS="110" in
advance or change SIOCKS after SIO is stopped.
At the same time, SIOS is cleared to "0". However, the values set for SIOEDG, SIOCKS and SIODIR are maintained.
SIOM
SIOS
Transfer edge selection
Serial clock selection [Hz]
Transfer format (MSB/LSB) selec-
tion
Transfer operation start/stop in-
struction
Transfer mode selection and
operation
SIOEDG
R/W
7
0
6
0
SIOCKS
R/W
5
0
Page 242
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
0: Receive data at a rising edge and transmit data at a falling edge
1: Transmit data at a rising edge and receive data at a falling edge
LSB first (transfer from bit 0)
MSB first (transfer from bit 7)
0: Operation stop (reserved stop)
1: Operation start
Operation stop (forced stop)
8-bit transmit mode
8-bit receive mode
8-bit transmit and receive mode
NORMAL1/2 or IDLE1/2 mode
4
0
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
SIODIR
R/W
3
0
9
6
5
4
3
2
External clock input
SIOS
R/W
2
0
SLOW1/2 or SLEEP1 mode
1
0
TMP89FM82T
fs/2
-
-
-
-
-
-
SIOM
3
R/W
0
0

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