at90ls4433 ATMEL Corporation, at90ls4433 Datasheet - Page 93

• Manufacturer Part Number: at90ls4433
• Description: At90s4433 8-bit Avr Microcontroller With 4k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Serial Downloading
Serial Programming
Algorithm
1042H–AVR–04/03
Both the Program and Data memory arrays can be programmed using the SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and
MISO (output) (see Figure 66). After RESET is set low, the Programming Enable
instruction needs to be executed first before program/erase instructions can be
executed.
Figure 66. Serial Programming and Verify
For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction
and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc-
tion turns the content of every memory location in both the program and EEPROM
arrays into $FF.
The Program and EEPROM memory arrays have separate address spaces: 0000 to
$07FF for Program memory and $0000 to $00FF for EEPROM memory.
Either an external system clock is supplied at pin XTAL1 or a crystal needs to be con-
nected across pins XTAL1 and XTAL2. The minimum low and high periods for the serial
clock (SCK) input are defined as follows:
When writing serial data to the AT90S4433, data is clocked on the rising edge of CLK.
When reading data from the AT90S4433, data is clocked on the falling edge of CLK.
See Figure 67, Figure 68 and Table 36 for details.
To program and verify the AT90S4433 in the Serial Programming mode, the following
sequence is recommended (see 4-byte instruction formats in Table 35):
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Program-
3. The serial programming instructions will not work if the communication is out of
Low: > 2 XTAL1 clock cycles
High: > 2 XTAL1 clock cycles
Apply power between V
crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to
the XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is
held low during Power-up. In this case, RESET must be given a positive pulse of
at least two XTAL1 cycles’ duration after SCK has been set to “0”.
ming Enable serial instruction to pin MOSI/PB3.
synchronization. When in sync, the second byte ($53) will echo back when issu-
DATA OUT
CLOCK IN
INSTR. IN
CLOCK
INPUT
GND
CC
and GND while RESET and SCK are set to “0”. If a
PB4(MISO)
PB3(MOSI)
PB5(SCK)
RESET
XTAL1
GND
AT90S/LS4433
VCC
4.0 - 6.0 V (AT90S4433)
2.7 - 6.0 V (AT90LS4433)
AT90S/LS4433
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