at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 110

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

13.7
110
Enhanced Resolution
AT90PWM81
Lamp Ballast applications need an enhanced resolution down to 50Hz. The method to improve the normal
resolution is based on Flank Width Modulation (also called Fractional Divider). Cycles are grouped into
frames of 16 cycles. Cycles are modulated by a sequence given by the fractional divider number. The
resulting output frequency is the average of the frequencies in the frame. The fractional divider (d) is
given by OCRnRB[15:12].
The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0) and
PSCOUTn1 On Time + Dead Time (OT1+DT1) values. These values are 12 bits numbers. The frequency
adjustment can only be done in steps like the dedicated counters. The step width is defined as the fre-
quency difference between two neighboring PSC frequencies.
It is possible to apply the Flank Width Modulation (FWM) on RB, RB+RA, SB, SB+SA. The selection is
done bit the bits PBFMn0 and PBFMn.
According to the ramp mode and the enhanced resolution mode (defined by PBFMn1:0), the frequency
difference Δf can take three different values:
with k is the number of CLK
with f
Example, in normal mode, with maximum operating frequency 160 kHz and f
The resulting resolution is Delta F equals 64MHz / 400 / 401 = 400 Hz.
In enhanced mode, the output frequency is the average of the frame formed by the 16 consecutive cycles.
f
Then the frequency resolution is divided by 16. In the example above, the resolution equals 25 Hz.
b1
and f
OP
b2
is the output operating frequency.
are two neighboring base frequencies.
PSC
Δf1
Δf2
period in a PSC cycle and is given by the following formula:
=
=
f
AVERAGE
f
f1 f2
f1 f2
AVERAGE
–
–
=
=
=
=
16 d
-------------- -
f
----------
f
----------
PSC
PSC
k
k
k
16 d
-------------- -
16
Δf
–
=
16
–
–
–
=
f
----------
f
×
----------- -
k
----------- -
k
PSC
f
f
OP
PSC
PSC
0
×
+
+
f
--------- -
PLL
k
f
1
2
b1
=
=
+
+
----- -
16
----- -
16
f
f
d
d
PSC
PSC
×
×
----------- -
k
f
f
×
×
b2
PLL
+
-------------------
k k
-------------------
k k
1
(
(
1
2
+
+
1
2
)
)
PLL
= 64 Mhz, k equals 400.
7734M–AVR–03/10