at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 209

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

18.5.1
18.5.2
18.6
7734M–AVR–03/10
ADC Noise Canceler
ADC Input Channels
ADC Voltage Reference
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must
be taken when updating the ADMUX Register, in order to control which conversion will be affected by
the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX
Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new
settings. ADMUX can be safely updated in the following ways:
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
When changing channel selections, the user should observe the following guidelines to ensure that the
correct channel is selected:
The reference voltage for the ADC (V
nels that exceed V
2.56V reference, or external AREF pin.
AV
the internal bandgap reference (V
to the ADC, the reference voltage can be made more immune to noise by connecting a capacitor between
the AREF pin and ground. V
Note that V
The user may switch between AV
sion result after switching reference voltage source may be inaccurate, and the user is advised to discard
this result.
If differential channels are used, the selected reference should not be closer to AV
Table 25-5 on page
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced
from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction
and Idle mode. To make use of this feature, the following procedure should be used:
• In Single Conversion mode, always select the channel before starting the conversion. The channel
• In Free Running mode, always select the channel before starting the first conversion. The channel
• In Free Running mode, because the amplifier clear the ADSC bit at the end of an amplified
selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest
method is to wait for the conversion to complete before changing the channel selection.
selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest
method is to wait for the first conversion to complete, and then change the channel selection. Since the
next conversion has already started automatically, the next result will reflect the previous channel
selection. Subsequent conversions will reflect the new channel selection.
conversion, it is not possible to use the free running mode, unless ADSC bit is set again by soft at the
end of each conversion.
CC
a.
b.
c.
is connected to the ADC through a passive switch. The internal 2.56V reference is generated from
When ADATE or ADEN is cleared.
During conversion, minimum one ADC clock cycle after the trigger event.
After a conversion, before the interrupt flag used as trigger source is cleared.
REF
is a high impedant source, and only a capacitive load should be connected in a system.
REF
281.
will result in codes close to 0x3FF. V
REF
can also be measured at the AREF pin with a high impedant voltmeter.
BG
CC,
) through an internal amplifier. If the external AREF pin is connected
AREF pin and 2.56V as reference selection. The first ADC conver-
REF
) indicates the conversion range for the ADC. Single ended chan-
REF
can be selected as either AV
AT90PWM81
CC
than indicated in
CC
, internal
209