at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 13

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

4.8
4.8.1
7734M–AVR–03/10
Reset and Interrupt Handling
Interrupt Behavior
Figure 4-4.
Figure 4-5
tion using two register operands is executed, and the result is stored back to the destination register.
Figure 4-5.
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each
have a separate program vector in the program memory space. All interrupts are assigned individual
enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status
Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be
automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security. See the section
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vec-
tors. The complete list of vectors is shown in
levels of the different interrupts. The lower the address the higher is the priority level. RESET has the
highest priority, and next is PSC2 CAPT – the PSC2 Capture Event. The Interrupt Vectors can be moved
to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).
Refer to
the Boot Flash section by programming the BOOTRST Fuse, see
Write Self-Programming” on page
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruc-
tion – RETI – is executed.
Register Operands Fetch
“Interrupts” on page 61
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
shows the internal timing concept for the Register File. In a single clock cycle an ALU opera-
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
clk
clk
CPU
CPU
for more information. The Reset Vector can also be moved to the start of
“Memory Programming” on page 247
232.
T1
“Interrupts” on page
T1
T2
T2
61. The list also determines the priority
“Boot Loader Support – Read-While-
for details.
AT90PWM81
T3
T3
T4
T4
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