ep9315 Cirrus Logic, Inc., ep9315 Datasheet
ep9315
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ep9315 Summary of contents
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... I-Cache 16KB 16KB Boot MMU ROM SRAM & Flash I/F Unified PCMCIA SDRAM I/F MEMORY AND STORAGE © Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Data Sheet Clocks & Timers TM Interrupts & GPIO Keypad & Touch Bus Screen I/F Bridge Processor Bus Video/LCD ...
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... A three-port USB 2.0 Full Speed Host (OHCI) (12 Mbits per second) and three UARTs are included as well. The EP9315 is a high-performance, low-power, RISC- based, single-chip computer built around an ARM920T microprocessor core with a maximum operating clock rate of 200 MHz (184 MHz for industrial conditions). The ARM core operates from a 1 ...
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... AC’97 ........................................................................................................................ 51 LCD Interface ............................................................................................................ 52 ADC ........................................................................................................................... 53 JTAG .......................................................................................................................... 54 352 Pin BGA Package Outline .......................................................................55 352-Ball PBGA Diagram ........................................................................................... 55 352 Pin BGA Pinout (Bottom View) ........................................................................... 56 Acronyms and Abbreviations ........................................................................63 Units of Measurement .....................................................................................63 ORDERING INFORMATION ............................................................................64 DS638PP4 © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor EP9315 3 ...
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... EP9315 Enhanced Universal Platform SOC Processor List of Figures Figure 1. Timing Diagram Drawing Key ................................................................................. 14 Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 15 Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 16 Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 17 Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 18 Figure 6 ...
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... Table Q. Reset and Power Management Pin Assignments ................................................... 11 Table R. Hardware Debug Interface ...................................................................................... 11 Table S. PCMCIA Interface ................................................................................................... 11 Table R. 352 Pin Diagram Dimensions .................................................................................. 56 Table S. Pin Descriptions ..................................................................................................... 60 Table T. Pin Multiplex Usage Information ............................................................................. 62 DS638PP4 © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor EP9315 5 ...
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... EP9315 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP9315 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’ ...
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... I2S Master Clock) AC'97 Reset AC'97 Reset I2S Master Clock AC'97 Bit Clock I2S Serial Clock AC'97 Frame AC'97 Frame I2S Frame Clock Clock Clock AC'97 Serial AC'97 Serial Input I2S Serial Input Input AC'97 Serial AC'97 Serial I2S Serial Output Output Output EP9315 ® and 2 S ports Mode 7 ...
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... Composite Blank BRIGHT Pulse Width Modulated Brightness Graphics Accelerator The EP9315 contains a hardware graphics acceleration engine that improves graphic performance by handling block copy, block fill and hardware line draw operations. The Graphics Accelerator is used in the system to off- load graphics operations from the processor. ...
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... Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Table J. Triple Port USB Host Pin Assignments Pin Name - Description USB Positive signals USB Negative Signals Pin Name - Description General Two-Wire Interface Clock Purpose I/O General Two-Wire Interface Data Purpose I/O EP9315 Alternative Usage 9 ...
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... This compensation is accurate to ± 1.24 sec/month. Note: A real time clock must be connected to RTCXTALI or the EP9315 device will not boot. Table L. Real-Time Clock with Pin Assignments Pin Mnemonic Pin Name - Description RTCXTALI Real-Time Clock Oscillator Input ...
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... DMA channel, source and destination addressing can be independently programmed to increment, decrement, or stay at the same value. All DMA addresses are physical, not virtual addresses. PCMCIA Interface The EP9315 has a single PCMCIA port which can be used to access either 8 or 16-bit devices. Pin Mnemonic VS1 VS2 ...
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... EP9315 Enhanced Universal Platform SOC Processor Electrical Specifications Absolute Maximum Ratings (All grounds = 0 V, all voltages with respect Parameter Power Supplies Total Power Dissipation Input Current per Pin, DC (Except supply pins) Output current per pin, DC Digital Input voltage Storage temperature Note: 1 ...
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... Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Min Max 0.85 × RVDD 0.15 × RVDD 0.65 × RVDD V VDD + 0.3 ih 0.35 × RVDD V -0 -10 il Min Typ Max - 190 240 - 3 EP9315 Unit µA µA Unit Table ...
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... EP9315 Enhanced Universal Platform SOC Processor Timings Timing Diagram Conventions This data sheet contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated. ...
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... DQh t DAs t DAh OP-Code © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Min Typ Max ( HCLK ( HCLK - clk_low clk_high EP9315 Unit ...
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... EP9315 Enhanced Universal Platform SOC Processor SDRAM Burst Read Cycle SDCLK t d SDCSn RASn CASn SDWEn t DQd DQMn DQMn clk_low DAs DAh n t DAs Figure 3. SDRAM Burst Read Cycle Timing Measurement © ...
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... SDRAM Burst Write Cycle SDCLK t d SDCSn RASn CASn SDWEn DQMn DS638PP4 t clk_low Figure 4. SDRAM Burst Write Cycle Timing Measurement © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor t clk_high t clkrf EP9315 ...
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... EP9315 Enhanced Universal Platform SOC Processor SDRAM Auto Refresh Cycle SDCLK SDCSn RASn CASn SDWEn Note: Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access Figure 5. SDRAM Auto Refresh Cycle Timing Measurement 18 t clk_low © ...
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... RDpw t - RDd t - DQMd + DAs HCLK t 0 DAh t ADs t RDd t DQMd © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Typ Max - - - - × (WST1 + HCLK - ADh t RDd t t DAs EP9315 Unit DAh 19 ...
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... EP9315 Enhanced Universal Platform SOC Processor Static Memory Single Word Write Cycle Parameter AD setup to WRn assert time AD hold from WRn deassert time WRn deassert to CSn deassert time CSn to WRn assert delay time WRn assert time CSn to DQMn assert delay time WRn deassert to DA transition time ...
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... Enhanced Universal Platform SOC Processor Typ Max - - × (WST1 + HCLK × (WST1 + HCLK × (WST1 + HCLK - - × (4 × WST1 + 5) - HCLK - AD2 AD3 t RDd DAh1 DAh1 t t DAs1 EP9315 Unit ADh t DAh2 DAs2 21 ...
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... EP9315 Enhanced Universal Platform SOC Processor Static Memory 32-bit Write on 8-bit External Bus Parameter AD setup to WRn assert time WRn/DQMn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time WRn assert time ...
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... Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Typ Max - - × (WST1 + HCLK × (WST1 + HCLK - - × ((2 × WST1 HCLK - ADd2 t RDh t DQMh t t DAh1 DAs2 EP9315 Unit ADh t DAh2 23 ...
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... EP9315 Enhanced Universal Platform SOC Processor Static Memory 32-bit Write on 16-bit External Bus Parameter AD setup to WRn assert time WRn/DQMn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time WRn assert time ...
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... Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Typ Max × (WST1 + 1) t HCLK × (WST2 + 1) t HCLK × (WST1 + 2) t HCLK - - - - - - - t t ADd2 ADd3 t t DAh1 DAh1 t t DAs1 DAs2 EP9315 Unit - ADh t DAh2 25 ...
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... EP9315 Enhanced Universal Platform SOC Processor Static Memory Burst Write Cycle Parameter AD setup to WRn assert time AD hold from WRn deassert time WRN/DQMn deassert to AD transition time CSn hold from WRn deassert time CSn to WRn assert delay time CSn to DQMn assert delay time ...
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... Min t - WAITd × WAITpw HCLK × CSnd HCLK t WAITd t WAITpw © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Typ Max × (WST1- HCLK × 510 t - HCLK × HCLK t CSnd EP9315 Unit ...
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... EP9315 Enhanced Universal Platform SOC Processor Static Memory Single Write Wait Cycle Parameter WAIT to WRn deassert delay time CSn assert to WAIT time WAIT assert time WAIT to CSn deassert delay time AD CSn WRn RDn DQMn DA WAIT Figure 15. Static Memory Single Write Wait Cycle Timing Measurement ...
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... IDCY is honored when going from a asynchronous device (CSx synchronous device (/SDCSy). AD CSnX CSnY WRn RDn DQMn DA WAIT Figure 16. Static Memory Turnaround Cycle Timing Measurement DS638PP4 Symbol Min t - BTcyc t BTcyc © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Typ Max × (IDCY+ HCLK EP9315 Unit ns 29 ...
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... EP9315 Enhanced Universal Platform SOC Processor PCMCIA Interface PCMCIA Read Cycle Parameter AD setup to signal transition time Attribute access time Attribute hold time Attribute space pre-charge delay time Common access time Common hold time Common space pre-charge delay time I/O access time I/O hold time ...
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... HCLK HCLK ( × HCLK HCLK ( × HCLK HCLK ( × t HCLK HCLK ( × HCLK HCLK ( × HCLK HCLK ( × t HCLK HCLK - - MCDh t DAfo EP9315 Unit - ...
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... EP9315 Enhanced Universal Platform SOC Processor IDE Interface Register Transfers Parameter Cycle time Address valid to DIORn / DIOWn setup DIORn / DIOWn pulse width 8-bit DIORn / DIOWn recovery time DIOWn data setup DIOWn data hold DIORn data setup DIORn data hold DIORn data high impedance state ...
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... IORDY is released prior to negation and may be asserted for no more than t A Figure 19. Register Transfer to/from Device © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor IORDY is released prior to negation A before asserting IORDY. RD EP9315 C 33 ...
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... EP9315 Enhanced Universal Platform SOC Processor PIO Data Transfers Parameter Cycle time Address valid to DIORn / DIOWn setup DIORn / DIOWn 16-bit DIORn / DIOWn recovery time DIOWn data setup DIOWn data hold DIORn data setup DIORn data hold DIORn data high impedance state ...
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... IORDY is released prior to negation and may be asserted for no more than t A Figure 20. PIO Data Transfer to/from Device © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor IORDY is released prior to negation A before asserting IORDY. RD EP9315 C 35 ...
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... EP9315 Enhanced Universal Platform SOC Processor Ultra DMA Data Transfer Figure 21 through Figure 30 define the timings associated with all phases of Ultra DMA bursts. The following table contains the values for the timings for each of the Ultra DMA modes. Timing reference levels = 1.5 V ...
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... The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are not in effect until DMARQ and DMACKn are asserted. DS638PP4 t ACK ENV t ACK ENV t AZ ACK Figure 21. Initiating an Ultra DMA data-in Burst © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor ZAD t ZAD t t DVS DVH EP9315 37 ...
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... EP9315 Enhanced Universal Platform SOC Processor DSTROBE (device) t DVH DD (15:0) (device) DSTROBE (host (15:0) (host) Note: DD (15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device ...
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... DMARQ and DMACKn are negated. DS638PP4 ZAH t AZ Figure 24. Device Terminating an Ultra DMA data-in Burst © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor t MLI t ACK t ACK t IORDYZ t t DVS DVH CRC t ACK EP9315 39 ...
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... EP9315 Enhanced Universal Platform SOC Processor DMARQ (device) DMACKn (host) STOP (host) HDMARDYn (host) t RFS DSTROBE (device) DD (15:0) IDEDA[2:0] IDECS0n, IDECS1n Note: The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are no longer in effect after DMARQ and DMACKn are negated ...
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... The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are not in effect until DMARQ and DMACKn are asserted. DS638PP4 ACK ENV t ZIORDY t ACK t ACK Figure 26. Initiating an Ultra DMA data-out Burst © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor DVS EP9315 t DVH 41 ...
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... EP9315 Enhanced Universal Platform SOC Processor HSTROBE (host) t DVH DD (15:0) (host) HSTROBE (device (15:0) (device) Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host ...
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... DMARQ and DMACKn are negated. DS638PP4 Figure 29. Host Terminating an Ultra DMA data-out Burst © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor t MLI t ACK t IORDYZ t ACK t t DVS DVH CRC t ACK EP9315 43 ...
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... EP9315 Enhanced Universal Platform SOC Processor DMARQ (device) DMACKn (host) STOP (host) DDMARDYn (device) t RFS HSTROBE (host) DD (15:0) (host) IDEDA[2:0] IDECS0n, IDECS1n Note: The definitions for the DIOWn:STOP, IORDY:DDMARDYn:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are no longer in effect after DMARQ and DMACKn are negated. ...
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... Max 10 Mbit 100 Mbit 10 Mbit 100 Mbit mode mode mode mode 400 200 20 260 26 200 20 260 400 200 20 260 26 200 20 260 400 400 - - - - - - - - - - - - 300 300 EP9315 Unit ...
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... EP9315 Enhanced Universal Platform SOC Processor TXCLK t TXd TXD[3:0]/ TXEN/ TXERR RXCLK RXD[3:0]/ RXDVAL/ RXERR MDC t MDC_high MDIO t (Sourced MDC_per by STA) MDC MDIO (Sourced by PHY TX_high TX_low t TX_per t RXh t RXs t MDC_low t MDIOd Figure 31. Ethernet MAC Timing Measurement © Copyright 2005 Cirrus Logic (All Rights Reserved) ...
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... DS638PP4 Symbol t clk_per t clk_high t clk_low t clkrf t DMd t DMs t DMh t DSs t DSh © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Min Typ Max - tspix_clk - - (tspix_clk (tspix_clk EP9315 Unit ...
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... EP9315 Enhanced Universal Platform SOC Processor Texas Instruments’ Synchronous Serial Format t clk_per t clk_high SCLK SFRM SSPTXD/ MSB SSPRXD Microwire clk_per clkrf clk_high SCLK t clk_low SFRM MSB SSPTXD 8-bit control SSPRXD 48 t clkrf t clk_low LSB bits Figure 32. TI Single Transfer Timing Measurement ...
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... SCLK (SPO=1) t DMs SSPTXD MSB (master) t DMd t DSs SSPRXD MSB (slave) SFRM DS638PP4 t clk_per t clk_low t DMh t DSh Figure 34. SPI Format with SPH=1 Timing Measurement © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor t clkrf LSB LSB EP9315 49 ...
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... EP9315 Enhanced Universal Platform SOC Processor 2 Inter-IC Sound - I S Parameter SCLK cycle time SCLK high time SCLK low time SCLK rise/fall time SCLK to LRCLK assert delay time Hold between SCLK assert then LRCLK deassert or Hold between LRCLK deassert then SCLK assert ...
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... Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Min Typ Max - 81.4 - clk_per clk_low clkrf rfin rfout t rfin rfout EP9315 Unit ...
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... EP9315 Enhanced Universal Platform SOC Processor LCD Interface Parameter SPCLK rise/fall time SPCLK rising edge to control signal transition time SPCLK rising edge to data transition time Data valid time SPCLK HSYNC/ V_CSYNC/ BLANK/ BRIGHT [17:0] 52 Symbol t clkr clkrf t CD ...
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... Figure 38. ADC Transfer Function © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor Value Units 50K counts (approximate) 0.01% ±15 0.2% 3750 Samples per second 925 Samples per second 500 2 120 Vref EP9315 mV µs ms µV 53 ...
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... EP9315 Enhanced Universal Platform SOC Processor JTAG Parameter TCK clock period TCK clock high time TCK clock low time TMS / TDI to clock rising setup time Clock rising to TMS / TDI hold time JTAG port clock to output JTAG port high impedance to valid output ...
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... View) - (Bottom View) DS638PP4 - Figure 40. 352 Pin PBGA Pin Diagram © Copyright 2005 Cirrus Logic (All Rights Reserved) Enhanced Universal Platform SOC Processor S Ø 0. Ø 0.10 C Øb DETAIL B ddd C DETAIL A' EP9315 ...
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... EP9315 Enhanced Universal Platform SOC Processor Symbol 26. 23.80 D3 17.95 E 26. 23.80 E3 17.95 e ddd q Note: 1. Controlling Dimension: Millimeter. 2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls. 3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C. ...
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Y HSYNC DD[1] DD[12] P[2] AD[15] DA[6] DA[4] W P[12] P[9] DD[0] P[5] P[3] DA[7] DA[5] AD[1 V P[16] P[11] P[8] DD[15] DD[13] P[1] U AD[0] P[15] P[10] P[7] P[6] P[4] P[0] V_CSY DD[1 ...
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... EP9315 Enhanced Universal Platform SOC Processor Pin List The following Plastic Ball Grid Array (PBGA) ball assignment table is sorted in order of ball. Ball Signal Ball A1 CSN[ DA[28] E10 A3 AD[18] E11 A4 DD[8] E12 A5 DD[4] E13 A6 AD[17] E14 A7 RDN E15 A8 RXCLK E16 A9 MIIRXD[0] E17 A10 RXDVAL E18 A11 ...
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... CVDD Y1 HSYNC GND Y2 DD[1] RVDD Y3 DD[12] RVDD Y4 P[2] ROW[0] Y5 AD[15] ROW[3] Y6 DA[6] PLL_GND Y7 DA[4] ROW[5] Y8 AD[10] DA[8] Y9 DA[1] BLANK Y10 AD[8] P[13] Y11 IDEDA[0] SPCLK Y12 DTRN V_CSYNC Y13 TDO DD[14] Y14 BOOT[0] GND Y15 EEDAT CVDD Y16 ASDO RVDD Y17 SFRM1 GND Y18 RDLED GND Y19 USBP[1] RVDD Y20 ABITCLK EP9315 59 ...
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... Table summary of the EP9315 pin signals, which illustrates the pad type and pad pull type (if any). The symbols used in the table are defined as follows. (Note: A blank box means Not Applicable (NA) or, for Pull Type, No Pull (NP) ...
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... IDE Chip Select 1 output IDE 8ma IDE Read strobe output IDE 8ma IDE Write strobe output IDE 8ma IDE DMA acknowledge output IDE I PU IDE ready input Power P Digital power, 1.8V Power P Digital power, 3.3V Ground G Digital ground Ground G Digital ground EP9315 61 ...
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... EP9315 Enhanced Universal Platform SOC Processor Table T illustrates the pin signal multiplexing and configuration options. Physical Pin Name COL[7:0] ROW[7:0] EGPIO[0] EGPIO[1] EGPIO[2] EGPIO[3] EGPIO[4] EGPIO[5] EGPIO[6] EGPIO[7] EGPIO[8] EGPIO[9] EGPIO[10] EGPIO[11] EGPIO[12] EGPIO[13] EGPIO[14] EGPIO[15] ABITCLK ASYNC ASDO ASDI ARSTn ...
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... Celsius Hertz = cycle per second Kilobits per second Kilobyte KiloHertz = 1000 Hz Megabits per second MegaHertz = 1,000 kHz -6 microAmpere = 10 Ampere microsecond = 1,000 nanoseconds = 10 -3 milliAmpere = 10 Ampere millisecond = 1,000 microseconds = 10 -3 milliWatt = 10 Watts -9 nanosecond = 10 seconds -12 picoFarad = 10 Farads Volt Watt EP9315 -6 seconds -3 seconds 63 ...
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... The order numbers for the device are: EP9315-CB EP9315-CBZ -40 ° +85 ° C EP9315-IB -40 ° +85 ° C EP9315-IBZ EP9315 — CBZ Part Number Product Line: Embedded Processor Note the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative ...