mc9s08ll16 Freescale Semiconductor, Inc, mc9s08ll16 Datasheet

mc9s08ll16

Manufacturer Part Number

mc9s08ll16

Description

8-bit Hcs08 Central Processor Unit

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MC9S08LL16.pdf (36 pages)

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Download datasheet (539Kb)

Freescale Semiconductor

Data Sheet: Advance Information

MC9S08LL16 Series

Covers: MC9S08LL16 and

MC9S08LL8

Features

• 8-Bit HCS08 Central Processor Unit (CPU)

• On-Chip Memory

• Power-Saving Modes

• Clock Source Options

• System Protection

• Development Support

Preliminary

Subject to Change Without Notice

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

– Up to 20-MHz CPU at 3.6V to 1.8V across temperature range

– HC08 instruction set with added BGND instruction

– Support for up to 32 interrupt/reset sources

– Dual Array FLASH read/program/erase over full operating

– Random-access memory (RAM)

– Security circuitry to prevent unauthorized access to RAM and

– Two low power stop modes

– Reduced power wait mode

– Low power run and wait modes allow peripherals to run while

– Peripheral clock gating register can disable clocks to unused

– Very low power external oscillator that can be used in stop2 or

– 6 μs typical wake up time from stop3 mode

– Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal

– Internal Clock Source (ICS) — Internal clock source module

– Watchdog computer operating properly (COP) reset with

– Low-Voltage Warning with interrupt

– Low-Voltage Detection with reset or interrupt

– Illegal Opcode Detection with reset

– Illegal address Detection with reset

– FLASH block protection

– Single-wire background debug interface

of -40˚C to 85˚C

voltage and temperature

FLASH contents

voltage regulator is in standby

modules, thereby reducing currents.

stop3 modes to provide accurate clock source to real time

counter

or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz

to 16 MHz

containing a frequency-locked-loop (FLL) controlled by

internal or external reference; precision trimming of internal

reference allows 0.2% resolution and 2% deviation over

temperature and voltage; supports bus frequencies from 1MHz

to 10 MHz.

option to run from dedicated 1-kHz internal clock source or

bus clock

• Peripherals

• Input/Output

• Package Options

– Breakpoint capability to allow single breakpoint setting during

– On-chip in-circuit emulator (ICE) debug module containing

– LCD — 4x28 or 8x24 LCD driver with internal charge pump

– ADC — 8-channel, 12-bit resolution; 2.5 μs conversion time;

– ACMP — Analog comparator with selectable interrupt on

– SCI — Full duplex non-return to zero (NRZ); LIN master

– SPI— Full-duplex or single-wire bidirectional;

– IIC — IIC with up to 100 kbps with maximum bus loading;

– TPMx — Two 2-channel (TPM1 and TPM2); Selectable input

– TOD— (Time Of Day) 8-bit quarter second counter with

– 38 GPIOs, 2 output-only pins

– 8 KBI interrupts with selectable polarity

– Hysteresis and conﬁgurable pull up device on all input pins;

– 64-LQFP, 48-LQFP, 48-QFN

in-circuit debugging (plus two more breakpoints in on-chip

debug module)

three comparators and nine trigger modes. Eight deep FIFO for

storing change-of-ﬂow addresses and event-only data. Debug

module supports both tag and force breakpoints

and option to provide an internally regulated LCD reference

that can be trimmed for contrast control.

automatic compare function; temperature sensor; internal

bandgap reference channel; operation in stop3; fully functional

from 3.6V to 1.8V

rising, falling, or either edge of comparator output; compare

option to ﬁxed internal bandgap reference voltage; outputs can

be optionally routed to TPM module; operation in stop3

extended break generation; LIN slave extended break

detection; wake up on active edge

Double-buffered transmit and receive; Master or Slave mode;

MSB-ﬁrst or LSB-ﬁrst shifting

Multi-master operation; Programmable slave address;

Interrupt driven byte-by-byte data transfer; supports broadcast

mode and 10-bit addressing

capture, output compare, or buffered edge- or center-aligned

PWM on each channel;

match register; External clock source for precise time base,

time-of-day, calendar or task scheduling functions; Free

running on-chip low power oscillator (1 kHz) for cyclic

wake-up without external components.

Conﬁgurable slew rate and drive strength on all output pins.

Document Number: MC9S08LL16

64-LQFP

Case 840F

Rev. 2, 10/2008

48-LQFP

Case 932

48-QFN

1314

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