cop888fh National Semiconductor Corporation, cop888fh Datasheet - Page 27

• Manufacturer Part Number: cop888fh
• Description: 8-bit Cmos Rom Based Microcontrollers With 12k Memory, Comparators, Usart And Hardware Multiply/divide
• Manufacturer: National Semiconductor Corporation

Comparators
should also be disabled before entering either the HALT or
IDLE modes in order to save power. The configuration of the
CMPSL register is as follows:
CMPSL REGISTER (ADDRESS X’00B7)
The CMPSL register contains the following bits:
Rsvd
CMP20E Selects pin I6 as comparator 2 output provided
CMP2RD Comparator 2 result (this is a read only bit, which
CMP2EN Enable comparator 2
CMP10E Selects pin I3 as comparator 1 output provided
CMP1RD Comparator 1 result (this is a read only bit, which
CMP1EN Enable comparator 1
Note that the two unused bits of CMPSL may be used as
software flags.
Comparator outputs have the same spec as Ports L and G
except that the rise and fall times are symmetrical.
Multiply/Divide
This device contains a multiply/divide block. This block sup-
ports a 1 byte x 2 bytes (3 bytes result) multiply or a 3
bytes/2 bytes (2 bytes result) divide operation. The multiply
or divide operation is executed by setting control bits located
in the multiply/divide control register. The multiply or divide
operands must be placed into the appropriate memory
mapped locations before the operation is initiated.
CONTROL REGISTER BITS
The Multiply/Divide control register (MDCR) is located at ad-
dress xx9D. It has the following bit assignments:
Rsvd
DIVOVF Division Overflow (if the result of a division is
DIV
MULT
After the appropriate MDR registers are loaded, the MULT
and DIV start bits are set by the user to start a multiply or di-
vide operation. The division operation has priority, if both bits
are set simultaneously. The MULT and DIV bits are BOTH
automatically cleared by hardware at the end of a divide or
multiply operation. Each division operation causes the
DIVOVF flag to be set/reset as appropriate. The DIVOVF
flag is cleared following a multiplication operation. DIVOVF
is a read-only bit. The MULT and DIV bits are read/writable.
Bits 3–7 in MDCR should not be used, as the MULT and DIV
operations will change their values.
Rsvd
Bit 7
Rsvd
Bit 7
CMP20E
Rsvd
These bits are reserved and must be zero
greater than 16 bits or the user attempted to divide
by zero; 1 = error)
Start Division Operation (1 = start)
Start Multiplication Operation (1 = start)
These bit are reserved and must be zero
that CMP2EN is set to enable the comparator
will read as 0 if the comparator is not enabled)
that CMPIEN is set to enable the comparator
will read as 0 if the comparator is not enabled)
CMP2RD
Rsvd
CMP2EN
(Continued)
Rsvd
CMP10E
Rsvd
CMP1RD
OVF
DIV
DIV
CMP1EN
MULT
Bit 0
Rsvd
Bit 0
27
MULTIPLY/DIVIDE OPERATION
For the multiply operation, the multiplicand is placed at ad-
dresses xx9B and xx9C. The multiplier is placed at address
xx99. For the divide operation, the dividend is placed at ad-
dresses xx98 to xx9A and the divisor is placed at addresses
xx9B to xx9C. In both operations, all operands are inter-
preted as unsigned values. The divide or multiply operation
is started by setting the appropriate MDCR bit. If both the
MULT and DIV bits are set, the microcontroller performs a di-
vide operation. (The user is not required to read or clear the
DIVOVF error bit prior to beginning a new multiply/divide op-
eration. This bit is ignored during subsequent operations.
However, the next divide operation will overwrite the error
flag as appropriate, and the next multiply operation will clear
it.)
The multiply operation requires 1 instruction cycle to com-
plete. The divide operation requires 2 instruction cycles to
complete. A divide by zero or a division which produces an
overflow requires only 1 instruction cycle to execute. The
MDR1 through MDR5 registers and the MDCR register can
not be read from or written to during a multiply or divide op-
eration. Any attempt to write in to these registers will be ig-
nored. Any attempt to read these registers will return unde-
fined data.
The result of a multiply is placed in addresses xx99–xx9B.
The result of a divide is placed in a ddresses xx98–xx99. If a
division by zero is attempted or if the resulting quotient of a
divide operation is more than 16 bits long, then the DIVOVF
bit is set in the multiply/divide control register. The dividend
and the divisor are left unchanged. The divide operation al-
ways causes the DIVOVF flag to be set or reset as appropri-
ate. The DIVOVF flag is cleared following a multiply opera-
tion.
RESET STATE
A reset signal applied to the device during normal operation
has the following affects:
MDCR is cleared, and any operation in progress is stopped.
MDR1 through MDR5 are undefined.
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