cop884bc National Semiconductor Corporation, cop884bc Datasheet
cop884bc
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cop884bc Summary of contents
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... Memory, Comparators, and CAN Interface General Description The following part number is a pin count and tempera- ture variation of the COP884BC: COP885BC. The COP884BC ROM based microcontrollers are highly integrated COP8 ™ Feature core devices with 2k memory and advanced features including a CAN 2.0B (passive) in- terface and two Analog comparators ...
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Block Diagram www.national.com FIGURE 1. Block Diagram 2 DS012067-1 ...
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... Connection Diagrams Top View Order Number COP884BC-xxx/WM or COP684BC-xxx/WM See NS Package Number M28B Top View Order Number COP885BC-xxx/WM or COP685BC-xxx/WM See NS Package Number M20B FIGURE 2. Connection Diagrams Pinouts for 28-SO Package Port Type Pin G0 I/O G1 I/O G2 I/O G3 I/O G4 I I/O L1 I/O L2 I/O L3 I/O L4 I/O L5 I/O DS012067-2 L6 I/O D0 ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin DC Electrical Characteristics COP884BC: −40˚C T +85˚C A Parameter Operating Voltage Power Supply Ripple (Note 3) Supply Current ...
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... DC Electrical Characteristics COP884BC: −40˚C T +85˚C A Parameter Maximum Input Current without Latchup (Notes 8, 10) RAM Retention Voltage, V (Note 9) r Input Capacitance Load Capacitance on D2 Note 3: Maximum rate of voltage change must be less than 0.5 V/ms Note 4: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at V Note 5: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to V outputs and programmed low ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin DC Electrical Characteristics COP684BC: −55˚C T +125˚C A Parameter Operating ...
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... These two pins will not latch up. The voltage at the pins must be limited to less than 14V. Note 9: Condition and parameter valid only for part in HALT mode. Note 10: Parameter characterized but not tested. AC Electrical Characteristics COP684BC and COP884BC: −55˚C T +125˚C ...
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On-Chip Voltage Reference: −55˚C T +125˚C A Parameter Reference Voltage V REF Reference Supply Current Note 15: Reference supply I is supplied for information purposes only not tested. DD Comparator DC/AC Characteristics: 4.5V V 5.5V, −55˚C ...
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Typical Performance Characteristics Port D Source Current Ports G/L Source Current Ports G/L Weak Pull-Up Source Current −55˚C T +125˚C A Port D Sink Current DS012067-39 Port G/L Sink Current DS012067-41 Dynamic DS012067-43 9 DS012067-40 DS012067-42 ...
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Typical Performance Characteristics Idle CAN Tx0 Sink Current Pin Descriptions V and GND are the power supply pins. CC CKI is the clock input. The clock can come from a crystal oscillator (in conjunction with ...
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Pin Descriptions (Continued) registers associated with the G Port, a data register and a configuration register. Therefore, each of the 6 I/O bits (G0–G5) can be individually configured under software con- trol. Since input only pin and ...
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Functional Description The device has 64 bytes of RAM. Sixteen bytes of RAM are mapped as “registers” at addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and ...
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Oscillator Circuits (Continued) TABLE 1. Crystal Oscillator Configuration CKI Freq (pF) (pF) (MHz 30– 30– 200 100–150 0.455 Control Registers CNTRL Register (Address ...
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Timers (Continued) The timer block has three operating modes: Processor Inde- pendent PWM mode, External Event Counter mode, and Input Capture mode. The control bits T1C3, T1C2, and T1C1 allow selection of the different modes of operation. Mode 1. Processor ...
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Timers (Continued) FIGURE 10. Timer 1 in External Event Counter Mode FIGURE 11. Timer 1 in Input Capture Mode 15 DS012067-10 DS012067-11 www.national.com ...
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Timers (Continued) TIMER CONTROL FLAGS The control bits and their functions are summarized below. T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control T1C0 Timer Start/Stop control in Modes 1 and 2 (Pro- cessor Independent PWM and ...
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Timers (Continued) FIGURE 12. PWM Timer Capture Mode Block Diagram FIGURE 13. PWM Timer PWM Mode Block Diagram PWM Control Register (PWMCON) (Address X’00A2) Reserved ESEL PWPND PWIE PWMD PWON Bit 7 The PWMCON Register Bits are: Reserved This bit ...
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Timers (Continued) a fixed, non-programmable repetition rate of 255 PWM clock cycles. The timer is clocked by the output of an 8-bit, pro- grammable prescaler, which is clocked with the chip’s CKI frequency. Thus the PWM signal frequency can be ...
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Timers (Continued) becomes greater than RLON, the PWPND bit in the PWM control register is set to “1”. If the PWIE bit is also set to “1”, the PWPND bit is enabled to request an interrupt. It should be noted ...
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Power Save Modes (Continued) T0, are stopped. The power supply requirements of the microcontroller in this mode of operation are typically around 30% of normal power requirement of the microcontroller. As with the HALT mode, the device can be returned ...
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Multi-Input Wake Up (Continued) CAN RECEIVE WAKE UP The CAN Receive Wake Up source is always enabled and is always active on a falling edge of the CAN comparator output. There is no specific enable bit for the CAN Wake ...
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CAN Interface Block (Continued) Fully automatic transmission on error is supported for mes- sages not longer than two bytes. Messages which are longer than two bytes have to be processed by software. The interface is compatible with CAN Specification 2.0 ...
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Functional Block Description of the CAN Interface (Continued) Transceive Logic (TCL) The TCL is a state machine which incorporates the bit stuff logic and controls the output drivers, CRC logic and the Rx/Tx shift registers. It also controls the synchronization ...
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Functional Block Description of the CAN Interface In the case of an interrupt driven CAN interface, the calculation of the actual t INT: ; Interrupt latency = µs PUSH A,AB ; PUSH A ...
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Functional Block Description of the CAN Interface (Continued) RECEIVE IDENTIFIER HIGH (RID) (Address X’00B7) Reserved RID10 RID9 RID8 RID7 Bit 7 This register is read/write. Reserved Bit 7 is reserved and must be zero. RID10..RID4 Receive Identifier bits (upper bits) ...
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Functional Block Description of the CAN Interface (Continued) secutive “recessive” bits including the End of Frame, whereas the standard mode may time out after 128 x 11 recessive bits (e.g., bus idle). TRANSMIT CONTROL/STATUS (TCNTL) (00BB) NS1 NS0 TERR RERR ...
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Functional Block Description of the CAN Interface (Continued) until the transmission is completed, even if the user’s soft- ware has requested cancellation of the message error occurs during transmission, a requested cancellation may occur prior to the begining ...
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Functional Block Description of the CAN Interface (Continued) For information on bus synchronization and status of the CAN related registers after external reset refer to the RESET section. ON-CHIP VOLTAGE REFERENCE The on-chip voltage reference is a ratiometric reference. For ...
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Frame Formats (Continued) The control frames are: error/overload frame Note: This device cannot send an overload frame as a result of not being able to process all information. However, the device is able to recog- nize an overload condition and ...
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Frame Formats (Continued) A remote frame is identical to a data frame, except that the RTR bit is “recessive”, and there is no data field. IDE = Identifier Extension Bit The IDE bit in the standard format is transmitted “dominant”, ...
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Frame Formats (Continued) START OF FRAME (SOF) The Start of Frame indicates the beginning of data and remote frames. It consists of a single “dominant” bit. A node is only allowed to start transmission when the bus is idle. All ...
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Frame Formats (Continued) tive node detecting an error, starts transmitting an active error flag consisting of six “dominant” bits. This causes the destruction of the actual frame on the bus. The other nodes detect the error flag as either a ...
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Frame Formats (Continued) module 1 = error active transmitter detects bit error at t2 module 2 = error active receiver with a local fault at t1 module 3 = error active receiver detects stuff error at t2 FIGURE 27. Error ...
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Frame Formats (Continued) module 1 = error active receiver with a local fault at t1 module 2 = error passive transmitter detects bit error at t2 module 3 = error passive receiver detects stuff error at t2 FIGURE 28. Error ...
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Frame Formats (Continued) An error passive unit can participate in bus communication. However, if the unit detects an error it is not allowed to send an active error flag. The unit sends only a passive (“reces- sive”) error flag. A ...
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Frame Formats (Continued) • If only one device is on the bus and this device transmits a message, it will get no acknowledgment. This will be detected as an error and message will be repeated. When the device goes “error ...
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Frame Formats (Continued) Comparators The device has two differential comparators. Port L is used for the comparators. The output of the comparators is multi- plexed out to two pins. The following are the Port L assign- ments: L6 Comparator 2 ...
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Comparators (Continued) CMP1EN Enables comparator 1 (“1”=enable). If compara- tor 1 is disabled the associated L-pins can be used as standard I/O. Reserved This bit is reserved and should be zero. The Comparator Select/Control bits are cleared on RESET (the ...
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Interrupts (Continued) MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of ...
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Interrupts (Continued) An interrupt service routine typically ends with an RETI instruction. This instruction sets the GIE bit back to 1, pops the address stored on the stack, and restores that address to the program counter. Program execution then proceeds ...
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Interrupts (Continued) Arbitration Ranking Note 18 VIS page If, by accident, a VIS gets executed and no interrupt is active, ...
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Interrupts (Continued) www.national.com DS012067-78 FIGURE 36. VIS Operation DS012067-79 FIGURE 37. VIS Flowchart 42 ...
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Interrupts (Continued) Programming Example: External Interrupt PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD SBIT IEDG, CNTRL SBIT EXEN, PSW SBIT GIE, PSW WAIT: JP WAIT . . . .=0FF VIS . . . .=01FA .ADDRW SERVICE . . INT_EXIT: ...
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Interrupts (Continued) NON-MASKABLE INTERRUPT Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory- mapped and cannot be accessed directly by the software. The pending flag is reset to ...
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Detection of Illegal Conditions The device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading of undefined ROM gets zeroes. The opcode for software interrupt is zero. If the program ...
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MICROWIRE/PLUS (Continued) TABLE 10. MICROWIRE/PLUS Master Mode Clock Selection SL1 SL0 Where t is the instruction cycle clock c MICROWIRE/PLUS Slave Mode Operation In the MICROWIRE/PLUS Slave mode of operation the SK clock is ...
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Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents On-Chip RAM bytes (48 bytes Unused RAM Address Space (Reads As All Ones) 80 ...
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Addressing Modes (Continued) TRANSFER OF CONTROL ADDRESSING MODES Relative This mode is used for the JP instruction, with the instruction field being added to the program counter to get the new program location. JP has a range from −31 to ...
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Instruction Set (Continued) INSTRUCTION SET ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical EXclusive OR IFEQ ...
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Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No OPeration www.national.com [SP] PL, [SP−1] PU,SP−2, PC ...
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Instruction Execution Time Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the ...
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NIBBLE LOWER 52 ...
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... Mask Options The COP684BC and COP884BC mask programmable op- tions are shown below. The options are programmed at the same time as the ROM pattern submission. OPTION 1: CLOCK CONFIGURATION =1 Crystal Oscillator (CKI/10) G7 (CKO) is clock generator output to crystal/resonator CKI is the clock input OPTION 2: HALT =1 Enable HALT mode ...
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... COP8-NSASM, COP8C, and WCOP8 IDE.) • COP8-UTILS: Free set of COP8 assembly code ex- amples, device drivers, and utilities to speed up code development. TOOLS ORDERING NUMBERS FOR THE COP884BC/COP8885BC FAMILY DEVICES Vendor Tools National COP8-NSEVAL COP8-NSEVAL ...
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Development Tools Support OTP Programmers Contact vendor < Cost: Free $100 $100 - $300 $300 - $1k $1k - $3k $3k - $5k WHERE TO GET TOOLS Tools are ordered ...
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... Physical Dimensions Order Number COP884BC-xxx/M or COP684BC-xxx/M Order Number COP885BC-xxx/M or COP685BC-xxx/M www.national.com inches (millimeters) unless otherwise noted NS Package Number M28B NS Package Number M20B 56 ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...