cop884bc National Semiconductor Corporation, cop884bc Datasheet - Page 45

• Manufacturer Part Number: cop884bc
• Description: 8-bit Cmos Rom Based Microcontrollers With 2k Memory, Comparators, And Can Interface
• Manufacturer: National Semiconductor Corporation

Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of undefined ROM gets zeroes. The opcode for
software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt, thus
signaling that an illegal condition has occurred.
The subroutine stack grows down for each call (jump to
subroutine), interrupt, or PUSH, and grows up for each
return or POP. The stack pointer is initialized to RAM location
02F Hex during reset. Consequently, if there are more re-
turns than calls, the stack pointer will point to addresses 030
and 031 Hex (which are undefined RAM). Undefined RAM
from addresses 030 to 03F Hex is read as all 1’s, which in
turn will cause the program to return to address 7FFF Hex.
This is an undefined ROM location and the instruction
fetched (all 0’s) from this location will generate a software
interrupt signaling an illegal condition.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM.
2. Over “POP”ing the stack by having more returns than
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restart-
ing (this recovery program is probably similar to that follow-
ing reset, but might not contain the same program initializa-
tion procedures).
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications
interface. The MICROWIRE/PLUS capability enables the
device to interface with any of National Semiconductor’s
MICROWIRE peripherals (i.e., A/D converters, display driv-
ers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 38 shows
a block diagram of the MICROWlRE/PLUS logic.
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/ PLUS
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the MI-
CROWIRE arrangement with an external shift clock is called
the Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
master mode the SK clock rate is selected by the two bits,
SL0 and SL1, in the CNTRL register. Table 10 details the
different clock rates that may be selected.
calls.
45
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 39 shows how
two COP888 family microcontrollers and several peripherals
may be interconnected using the MICROWIRE/PLUS ar-
rangements.
Warning:
The SIO register should only be loaded when the SK clock is
low. Loading the SIO register while the SK clock is high will
result in undefined data in the SlO register. SK clock is
normally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is low.
MICROWIRE/PLUS Master Mode Operation
In the MlCROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. Table 11 summarizes the bit settings
required for Master or Slave mode of operation.
FIGURE 38. MICROWIRE/PLUS Block Diagram
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DS012067-37