cop884bc National Semiconductor Corporation, cop884bc Datasheet - Page 11

• Manufacturer Part Number: cop884bc
• Description: 8-bit Cmos Rom Based Microcontrollers With 2k Memory, Comparators, And Can Interface
• Manufacturer: National Semiconductor Corporation

Pin Descriptions
registers associated with the G Port, a data register and a
configuration register. Therefore, each of the 6 I/O bits
(G0–G5) can be individually configured under software con-
trol.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin the associated bits in the data and configu-
ration registers for G6 and G7 are used for special purpose
functions as outlined below. Reading the G6 and G7 data
bits will return zeroes.
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alter-
nate phase of the SK clock.
CAN pins: For the on-chip CAN interface this device has five
dedicated pins with the following features:
V
Rx0
Rx1
Tx0
Tx1
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated function:
G7 CKO Oscillator dedicated output
Port D is a 4-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs
(except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the
REF
G7
G6
external loads on this pin must ensure that the output voltages stay
above 0.8 V
keep the external loading on D2 to less than 1000 pF.
On-chip reference voltage with the value of V
CAN receive data input pin.
CAN receive data input pin.
CAN transmit data output pin. This pin may be put in
the TRI-STATE mode with the TXEN0 bit in the CAN
Bus control register.
CAN transmit data output pin. This pin may be put in
the TRI-STATE mode with the TXEN1 bit in the CAN
Bus control register.
CC
Config. Register
Alternate SK
to prevent the chip from entering special modes. Also
(Continued)
Data Register
HALT
IDLE
CC
/2
11
Functional Description
The architecture of the device utilizes a modified Harvard
architecture. With the Harvard architecture, the control store
program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own sepa-
rate addressing space with separate address buses. The
architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 02F with reset.
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory for the device consists of 2048 bytes of
ROM. These bytes may hold program instructions or con-
stant data (data tables tor the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS
instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X and SP pointers.
FIGURE 5. I/O Port Configurations
c
) cycle time.
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