cop8cfe9 National Semiconductor Corporation, cop8cfe9 Datasheet
cop8cfe9
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cop8cfe9 Summary of contents
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... COP8CFE9 8-Bit CMOS Flash Microcontroller with 8k Memory, Virtual EEPROM, and 10-Bit A/D General Description The COP8CFE9 Flash microcontroller is a highly integrated COP8 ™ Feature core device, with 8k Flash memory and advanced features including Virtual EEPROM, A/D, and High Speed Timers. This single-chip CMOS device is suited for ...
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Block Diagram Ordering Information COP8 CF Family and Feature Set Indicator www.national.com Part Numbering Scheme Program Program Memory Memory No. Of Pins Size Type Flash Pin ...
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Connection Diagrams Top View Plastic Chip Package See NS Package Number V44A Top View LLP Package See NS Package Number LQA44A 20026464 TSSOP Package See NS Package Number MTD48 20026455 3 20026459 Top View www.national.com ...
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Port Type Alt. Function L0 I/O MIWU L1 I/O MIWU L2 I/O MIWU L3 I/O MIWU L4 I/O MIWU or T2A L5 I/O MIWU or T2B L6 I/O MIWU L7 I/O MIWU G0 I/O INT a G1 I/O WDOUT G2 ...
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... General Description 1.1 EMI REDUCTION The COP8CFE9 device incorporates circuitry that guards against electromagnetic interference - an increasing problem in today’s microcontroller board designs. National’s patented EMI reduction technology offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) and internal Icc smoothing filters, to help circumvent many of the EMI issues influencing embedded control designs. National has achieved 15 dB– ...
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General Description 1.5.4 Bit-Level Control Bit-level control over many of the microcontroller’s I/O ports provides a flexible means to ease layout concerns and save board space. All members of the COP8 family provide the ability to set, reset and ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin Total Current into V Pin (Source) CC 2.0 Electrical Characteristics ...
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Electrical Characteristics TABLE 1. DC Electrical Characteristics (−40˚C Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Input Capacitance Voltage Force Execution from Boot ROM(Note 8) G6 Rise Time to Force Execution ...
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A/D Converter Electrical Characteristics (−40˚C Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Resolution DNL DNL INL INL Offset Error Offset Error Gain Error Gain Error Input Voltage Range Analog Input Leakage Current Analog Input ...
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Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Operating Voltage Power Supply Rise Time Power Supply Ripple (Note 2) Supply Current (Note 3) CKI = 10 MHz CKI = 3.33 MHz HALT Current with BOR ...
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AC Electrical Characteristics (−40˚C Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter MICROWIRE/PLUS Output Propagation Delay (t ) UPD Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer 1 Input High Time ...
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A/D Converter Electrical Characteristics (−40˚C Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Resolution DNL INL Offset Error Gain Error Input Voltage Range Analog Input Leakage Current Analog Input Resistance (Note 9) Analog Input Capacitance ...
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Pin Descriptions (Continued) CKI is the clock input. This can be connected (in conjunction with CKO external crystal circuit to form a crystal oscillator. See Oscillator Description section. RESET is the master reset input. See Reset description ...
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Pin Descriptions L3 Multi-Input Wake-up L2 Multi-Input Wake-up L1 Multi-Input Wake-up L0 Multi-Input Wake-up FIGURE 3. I/O Port Configurations FIGURE 4. I/O Port Configurations — Output Mode FIGURE 5. I/O Port Configurations — Input Mode www.national.com 3.1 EMULATION CONNECTION ...
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Functional Description RAM address 06F Hex. The SP is decremented as items are pushed onto the stack. SP points to the next available loca- tion on the stack. All the CPU registers are memory mapped with the excep- tion ...
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Functional Description 4.4.1 Virtual EEPROM The Flash memory and the User ISP functions (see Section 5.7), provide the user with the capability to use the flash program memory to back up user defined sections of RAM. This effectively provides ...
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... Functional Description ;options .endsect Example: The following sets a value in the Option Register and User Identification for a COP8CFE9HVA7. The Option Register bit values shown select options: Security disabled, WATCHDOG enabled HALT mode enabled and execution will commence from Flash Memory. .chip 8CFE ...
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Functional Description WATCHDOG service window of 64k T0 clock cycles. The Clock Monitor bit being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of ...
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Functional Description 4.9 CONTROL REGISTERS CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL Bit 7 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit ...
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In-System Programming 5.1 INTRODUCTION This device provides the capability to program the program memory while installed in an application board. This feature is called In System Programming (ISP). It provides a means of ISP by using the MICROWIRE/PLUS, or ...
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In-System Programming (Continued) 5.3.2 ISP Read Data Register The Read Data Register (ISPRD) contains the value read back from a read operation. This register can be accessed from either flash program memory or Boot ROM. This regis- ter is ...
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In-System Programming (Continued) 5.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM When using ISP, at some point, it will be necessary to maneuver between the flash program memory and the Boot ROM, even when using customized ...
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In-System Programming (Continued) 5.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET After programming the entire program memory, including options necessary to exit the Boot ROM and return to the flash program memory for program execution. Upon receipt ...
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In-System Programming (Continued) • Copy a block of data from program flash memory to RAM. The following table lists the User ISP/Virtual E required parameters and return data, if applicable. The com- www.national.com mand entry point is used as ...
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In-System Programming Command/ Command Function Label Entry Point cpgerase Page Erase 0x17 cmserase Mass Erase 0x1A creadbf Read Byte 0x11 cblockr Block Read 0x26 cwritebf Write Byte 0x14 cblockw Block Write 0x23 exit EXIT 0x62 (Continued) 2 TABLE 12. ...
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In-System Programming Register Name ISPADHI High byte of Flash Memory Address ISPADLO Low byte of Flash Memory Address ISPWR The user must store the byte to be written into this register before jumping into the write byte routine. ISPRD ...
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Timers The device contains a very versatile set of timers (T0, T1, and T2). Timers T1, and T2 and associated autoreload/ capture registers power up containing random data. 6.1 TIMER T0 (IDLE TIMER) The device supports applications that require ...
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Timers (Continued) 6.2 TIMER T1 AND TIMER T2 The device has a set of two powerful timer/counter blocks, T1, and T2. Since T1, and T2 are identical, except for the high speed operation of T2, all comments are equally ...
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Timers (Continued) FIGURE 15. Timer in External Event Counter Mode 6.2.4 Mode 3. Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block, Tx, in the input capture mode. In ...
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Timers (Continued) register. Any type of read/write operation, including SBIT and RBIT may be performed on this register in any operating mode. Mode TxC3 TxC2 ...
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Power Saving Features lator has a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop. The start-up time-out from the IDLE timer enables the clock signals to be ...
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Power Saving Features 7.3 MULTI-INPUT WAKE-UP The Multi-Input Wake-up feature is used to return (wake-up) the device from either the HALT or IDLE modes. Alternately Multi-Input Wake-up/Interrupt feature may also be used to generate edge selectable ...
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Power Saving Features 8.0 A/D Converter This device contains a 16-channel, multiplexed input, suc- cessive approximation, 10 bit Analog-to-Digital Converter. Pins AV and AGND are used for the voltage reference. CC 8.1 OPERATING MODES It supports both Single Ended ...
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A/D Converter (Continued) TABLE 17. ENAD Bit 7 Channel Select Mode Select Mux/Out Prescale ADCH3 ADCH2 ADCH1 ADCH0 ADMOD CHANNEL SELECT This 4-bit field selects one of sixteen channels to be the V The mode selection and the mux ...
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A/D Converter (Continued) TABLE 19. A/D Converter Channel Selection when the Multiplexor Output is Enabled Select Bits ADCH3 ADCH2 ADCH1 ...
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A/D Converter (Continued) FIGURE 20. A/D with Single Ended Mux Output Feature Enabled FIGURE 21. A/D with Differential Mux Output Feature Enabled MODE SELECT This 1-bit field is used to select the mode of operation (single ended or differential) ...
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A/D Converter (Continued) 8.2 A/D OPERATION The A/D conversion is completed within fifteen A/D converter clocks. The A/D Converter interface works as follows. Setting the ADBSY bit in the A/D control register ENAD initiates an A/D conversion. The conversion ...
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Interrupts 9.1 INTRODUCTION The device supports nine vectored interrupts. Interrupt sources include Timer 1, Timer 2, Timer T0, Port L Wake-up, Software Trap, MICROWIRE/PLUS, and External Input. All interrupts force a branch to location 00FF Hex in program memory. ...
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Interrupts (Continued) tion. If the next normally executed instruction skipped, the skip is performed before the pending interrupt is acknowledged. At the start of interrupt acknowledgment, the following ac- tions occur: 1. The GIE bit is ...
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Interrupts (Continued) ensure that execution is not erroneous, the routine should restore the program context and execute the RETI to return to the interrupted program. This technique can save up to fifty instruction cycles (t more, (50 µs at ...
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Interrupts (Continued) 9.4 NON-MASKABLE INTERRUPT 9.4.1 Pending Flag There is a pending flag bit associated with the non-maskable Software Trap interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending ...
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Interrupts (Continued) user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution. Under normal conditions, the STPND flag is reset by a RPND instruction in the Software Trap service ...
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Interrupts (Continued) . SERVICE: RBIT,EXPND,PSW . . . RET I 9.5 PORT L INTERRUPTS Port L provides the user with an additional eight fully select- able, edge sensitive interrupts which are all vectored into the same service subroutine. The ...
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WATCHDOG/CLOCK MONITOR WDSVR WDSVR Bit 7 Bit 10.1 CLOCK MONITOR The Clock Monitor aboard the device can be selected or deselected under program control. The Clock Monitor is guaranteed not to reject ...
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WATCHDOG/CLOCK MONITOR (Continued) 10.3 WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted: • Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET. • Following RESET, the ...
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MICROWIRE/PLUS TABLE 28. MICROWIRE/PLUS Master Mode Clock Select SL1 SL0 Where t is the instruction cycle clock C 11.1 MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to ...
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MICROWIRE/PLUS clock. The SIO register is shifted on each falling edge of the SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on the rising ...
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MICROWIRE/PLUS FIGURE 30. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High 13.0 Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents S/ADD REG ...
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Memory Map (Continued) Address Contents S/ADD REG xxE6 Timer T1 Autoload Register T1RB Lower Byte xxE7 Timer T1 Autoload Register T1RB Upper Byte xxE8 ICNTRL Register xxE9 MICROWIRE/PLUS Shift Register xxEA Timer T1 Lower Byte xxEB Timer T1 Upper ...
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Instruction Set (Continued) Reg/Data Contents Memory Before Accumulator 01 Hex Memory Location 87 Hex 0005 Hex B Pointer 05 Hex Register Indirect with Post-Incrementing/ Decrementing. The relevant memory address is specified by the contents of the ...
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Instruction Set (Continued) Jump Absolute Long. In this 3-byte instruction, 15 bits of the instruction opcode specify the new contents of the Pro- gram Counter. Example: Jump Absolute Long JMP 03625 Reg/ Contents Memory Before PCU 42 Hex PCL ...
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Instruction Set (Continued) If Equal (IFEQ) If Not Equal (IFNE) If Greater Than (IFGT) If Carry (IFC) If Not Carry (IFNC) If Bit (IFBIT Pointer Not Equal (IFBNE) And Skip if Zero (ANDSZ) Decrement Register and Skip ...
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Instruction Set (Continued) 13.6 INSTRUCTION SET SUMMARY ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical ...
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Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JSRB Addr Jump SubRoutine Boot ROM JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No ...
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Instruction Set (Continued) Register Indirect [ (Note 21) 1 (Note 21) 1/1 LD B,Imm LD B,Imm LD Mem,Imm 2/2 LD Reg,Imm IFEQ MD,Imm > Note 21: = Memory location addressed ...
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Nibble Lower 56 ...
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... SKFlash, COP8 Emulators, COP8-PM. Eval The ultimate information source for COP8 developers - Integrates with WCOP8 IDE. Organize and manage code, notes, datasheets, etc. Free Online Graphical IDE, featuring UNIS Processor Expert( Code Development Tool with Simulator - Develop applications, simulate and debug, download working code. ...
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Development Support IAR Embedded COP8-SW-EWCOP8 Workbench Tool EWCOP8-BL Set. Assembler-Only Version Hardware Emulation and Debug Tools Hardware COP8-EMFlash-00 Emulators COP8-DMFlash-00 COP8-IMFlash-00 Emulator Null COP8-EMFA-68N Target COP8-EMFA-28N Emulator Target COP8-EMFA-44P Package Adapters COP8-EMFA-68P NiceMon Debug COP8-SW-NMON Monitor Utility Development and ...
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... WCOP8 IDE and Emulator Debugger, with Assembler/ Linker/ CD-ROM Simulators/ Library Manager/ Compiler Demos/ Flash ISP and NiceMon Debugger Utilities/ Example Code/ etc. Includes all COP8 datasheets and documentation. Included with most tools from National. Unis Processor Processor Expert( from Unis Corporation - COP8 Code Generation and Simulation Expert tool with Graphical and Traditional user interfaces ...
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Development Support Hardware Tools for: Real-time Emulation; Target Hardware Debug; Target Design Test. Product COP8Flash COP8 In-Circuit Emulator for Flash Families. Windows based development and Emulators - real-time in-circuit emulation tool, with trace (EM=None; DM/IM=32k), s/w COP8-EMFlash breakpoints (DM=16, ...
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Development Support Vendor Home Office KANDA Systems Unit 17 -18 LTD. Glanyrafon Enterprise Park, Aberystwyth, Ceredigion, SY23 3JQ, UK Tel: +44 1970 621041 Fax: +44 1970 621040 K and K Kaergaardsvej 42 DK-8355 Development ApS Solbjerg Denmark Fax: +45-8692-8500 ...
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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted LLP Package (LQA) Order Number COP8CFE9HLQ8 NS Package Number LQA44A TSSOP Package (MTD) Order Number COP8CFE9IMT8 NS Package Number MTD48 62 ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted (Continued) Plastic Leaded Chip Carrier (VA) Order Number COP8CFE9HVA8 NS Package Number V44A 2. A critical component is any component of a life ...