cop8cfe9 National Semiconductor Corporation, cop8cfe9 Datasheet - Page 26

• Manufacturer Part Number: cop8cfe9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, And 10-bit A/d
• Manufacturer: National Semiconductor Corporation

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ISPADHI
ISPADLO
ISPWR
ISPRD
ISPKEY
BYTECOUNTLO
PGMTIM
Confirmation Code
KEY
5.0 In-System Programming
5.9 RESTRICTIONS ON SOFTWARE WHEN CALLING
ISP ROUTINES IN BOOT ROM
1. The hardware will disable interrupts from occurring. The
2. The security feature in the MICROWIRE/PLUS ISP is
3. When using any of the ISP functions in Boot ROM, the
4. Block Writes can start anywhere in the page of Flash
5. The user must ensure that a page erase or a mass
hardware will leave the GIE bit in its current state, and if
set, the hardware interrupts will occur when execution is
returned to Flash Memory. Subsequent interrupts, dur-
ing ISP operation, from the same interrupt source will be
lost. Interrupts may occur between setting the KEY
and executing the JSRB instruction. In this case, the
KEY will expire before the JSRB is executed. It is,
therefore, recommended that the software globally
disable interrupts before setting the Key.
guaranteed by software and not hardware. When ex-
ecuting the MICROWIRE/PLUS ISP routine, the security
bit is checked prior to performing all instructions. Only
the mass erase command, write PGMTIM register, and
reading the Option register is permitted within the
MICROWIRE/PLUS ISP routine. When the user is per-
forming his own ISP, all commands are permitted. The
entry points from the user’s ISP code do not check for
security. It is the burden of the user to guarantee his own
security. See the Security bit description in 4.5 OPTION
REGISTER for more details on security.
ISP routines will service the WATCHDOG within the
selected upper window. Upon return to flash memory,
the WATCHDOG is serviced, the lower window is en-
abled, and the user can service the WATCHDOG any-
time following exit from Boot ROM, but must service it
within the selected upper window to avoid a WATCH-
DOG error.
memory, but cannot cross half page or full page bound-
aries.
erase is executed between two consecutive writes to
Register
Name
High byte of Flash Memory Address
Low byte of Flash Memory Address
The user must store the byte to be written into this register before jumping into the
write byte routine.
Data will be returned to this register after the read byte routine execution.
The ISPKEY Register is required to validate the JSRB instruction and must be loaded
within 6 instruction cycles before the JSRB.
Holds the count of the number of bytes to be read or written in block operations.
Write Timing Register. This register must be loaded, by the user, with the proper value
before execution of any USER ISP Write or Erase operation. Refer to Table 9 for the
correct value.
The user must place this code in the accumulator before execution of a Flash Memory
Mass Erase command.
Must be transferred to the ISPKEY register before execution of a JSRB instruction.
TABLE 13. Register and Bit Name Definitions
(Continued)
26
Purpose
5.10 FLASH MEMORY DURABILITY CONSIDERATIONS
The endurance of the Flash Memory (number of possible
Erase/Write cycles) is a function of the erase time and the
lowest temperature at which the erasure occurs. If the device
is to be used at low temperature, additional erase operations
can be used to extend the erase time. The user can deter-
mine how many times to erase a page based on what
endurance is desired for the application (e.g. four page
erase cycles, each time a page erase is done, may be
required to achieve the typical 100k Erase/Write cycles in an
application which may be operating down to 0˚C). Also, the
customer can verify that the entire page is erased, with
software, and request additional erase operations if desired.
Erase
Time
1 ms
2 ms
3 ms
4 ms
5 ms
6 ms
7 ms
8 ms
the same location in Flash memory. Two writes to
the same location without an intervening erase will
produce unpredicatable results including possible
disturbance of unassociated locations.
TABLE 14. Typical Flash Memory Endurance
Low End of Operating Temp Range
−40˚C
100k
60k
60k
60k
60k
70k
80k
90k
−20˚C
100k
60k
60k
60k
60k
70k
80k
90k
100k
100k
100k
100k
100k
0˚C
60k
60k
60k
25˚C
100k
100k
100k
100k
100k
100k
100k
100k
Location
>
100k
100k
100k
100k
100k
100k
100k
100k
0xAB
0xAA
RAM
0xA9
0xA8
0xE2
0xF1
0xE1
0x98
25˚C
A