cop8cfe9 National Semiconductor Corporation, cop8cfe9 Datasheet - Page 29

• Manufacturer Part Number: cop8cfe9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, And 10-bit A/d
• Manufacturer: National Semiconductor Corporation

6.0 Timers
6.2.4 Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode. In this mode, the reload registers serve
as independent capture registers, capturing the contents of
the timer when an external event occurs (transition on the
timer input pin). The capture registers can be read while
maintaining count, a feature that lets the user measure
elapsed time and time between events. By saving the timer
value when the external event occurs, the time of the exter-
nal event is recorded. Most microcontrollers have a latency
time because they cannot determine the timer value when
the external event occurs. The capture register eliminates
the latency time, thereby allowing the applications program
to retrieve the timer value stored in the capture register.
In this mode, the timer Tx is constantly running at the fixed t
or MCLK rate. The two registers, RxA and RxB, act as
capture registers. Each register also acts in conjunction with
a pin. The register RxA acts in conjunction with the TxA pin
and the register RxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin after synchro-
nization to the appropriate internal clock (t
trol bits, TxC3, TxC2 and TxC1, allow the trigger events to be
specified either as a positive or a negative edge. The trigger
condition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
sequently, the TxC0 control bit should be reset when enter-
FIGURE 15. Timer in External Event Counter Mode
(Continued)
C
or MCLK). Con-
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ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 16 shows a block diagram of the timer T1 in Input
Capture mode. T2 is identical to T1.
6.3 TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
The timer mode control bits (TxC3, TxC2 and TxC1) are
detailed in Table 16 .
When the high speed timer is counting in high speed mode,
directly altering the contents of the timer upper or lower
registers, the PWM outputs or the reload registers is not
recommended. Bit operations can be particularly problem-
atic. Since any of these six registers or the PWM outputs can
change as many as ten times in a single instruction cycle,
performing an SBIT or RBIT operation with the timer running
can produce unpredictable results. The recommended pro-
cedure is to stop the timer, perform any changes to the timer,
the PWM outputs or reload register values, and then re-start
the timer. This warning does not apply to the timer control
TxC3
TxC2
TxC1
TxC0
TxPNDA Timer Interrupt Pending Flag
TxENA
TxPNDB Timer Interrupt Pending Flag
TxENB
FIGURE 16. Timer in Input Capture Mode
Timer mode control
Timer mode control
Timer mode control
Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in Mode
3 (Input Capture)
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
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20026469