scf5250 Freescale Semiconductor, Inc, scf5250 Datasheet
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... Freescale Semiconductor Data Sheet SCF5250 Integrated ColdFire® Microprocessor Data Sheet 1 Introduction This document provides an overview of the SCF5250 ® ColdFire processor and general descriptions of SCF5250 features and its various modules. The SCF5250 was designed as a system controller/decoder for compressed audio music players, especially portable and automotive CD and hard disk drive players ...
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... Introduction SCF5250 to replace both the microcontroller and the DSP in certain applications. Most peripheral pins can also be remapped as General Purpose I/O pins. 1.1 Orderable Part Numbers 1.1.1 Orderable Part Table Orderable Part Maximum Clock Number Frequency SCF5250AG120 120 MHz SCF5250CAG120 120 MHz SCF5250VM120 120 MHz 1 ...
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... SDRAM Controller The SCF5250 SDRAM controller provides a glueless interface for one bank of SDRAM (256 Mbits). The controller supports a 16-bit data bus. A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards. The controller operates in page mode, non-page mode, and burst-page mode and supports SDRAMS ...
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... Maximum sampling frequency is determined by maximum frequency on bit clock input. This is 1/3 the frequency of the internal system clock. 1.2.10 IEC958 Digital Audio Interfaces The SCF5250 has one digital audio input interface, and one digital audio output interface. The single output carries the consumer “c” channel. 1.2.11 Audio Bus The audio interfaces connect to an internal bus that carries all audio data ...
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... IDE and SmartMedia Interfaces The SCF5250 system bus allows connection of an IDE hard disk drive or SmartMedia flash card with a minimum of external hardware. The external hardware consists of bus buffers for address and data and are intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the IDE bus ...
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... All interrupts are autovectored and interrupt levels are programmable. 1.2.22 JTAG To help with system diagnostics and manufacturing testing, the SCF5250 includes dedicated user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability, often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1A standard ...
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... LC oscillator. 1.2.25 Boot ROM The boot ROM on the SCF5250 serves to boot the CPU in designs which do not have external Flash memory or ROM. Typically this occurs in systems which have a separate MCU to control the system, and/or the SCF5250 is used as a stand-alone decoder ...
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... Documentation Table 2 lists the documents that provide a complete description of the SCF5250 and are required to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home page on the Internet; http://e-www.Freescale.com/ (the source for the latest information). ...
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... Document Name CFPRM/D ColdFire2UM ColdFire2UMAD SCF5250UM 4 Signal Descriptions 4.1 Introduction This section describes the SCF5250 input and output signals. The signal descriptions as shown in Table 2-A are grouped according to relevant functionality. Signal Name Address A[24:1] A[23]/GPO54 Read-write control R/W Output enable OE Data D[31:16] Synchronous row address SDRAS/GPIO59 ...
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... LRCK1/GPIO19 LRCK2/GPIO23 LRCK3/GPIO43/AUDIO_CLOCK Bit clock SCLK1/GPIO20 SCLK2/GPIO22 SCLK3/GPIO35 SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 10 Table 3. SCF5250 Signal Index (continued) Mnemonic There is 1 ISA bus read strobe and 1 ISA bus write strobe. They allow connection of one independent ISA bus peripherals, e.g. an IDE slave device ...
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... Crystal out CROUT Reset In RSTI Freescale Test Mode TEST[2:0] Linear regulator output LINOUT SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Table 3. SCF5250 Signal Index (continued) Mnemonic error flag serial in C-flag serial in audio interfaces subcode clock audio interfaces subcode sync ...
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... Multiplex Control Registers, GPIO-FUNCTION, GPIO1-FUNCTION and PIN-CONFIG. • At Power-on reset, all pins are set to their primary function. 4.3 SCF5250 Bus Signals These signals provide the external bus interface to the SCF5250. SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 12 Table 3. SCF5250 Signal Index (continued) Mnemonic Input, typically I/O supply (3 ...
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... Data Bus The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the SCF5250 on the rising clock edge. The data bus uses a default configuration if none of the chip-selects or DRAM bank match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or operand size ...
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... The active low chip selects can be used to access asynchronous memories. The interface is glueless. 4.6 ISA bus The SCF5250 supports an ISA bus. Using the ISA bus protocol, reads and writes for one ISA bus peripheral is possible. IDE-DIOR/GPIO31 and IDE-DIOW/GPIO32 are the read and write strobe. The peripheral can insert wait states by pulling IDE-IORDY/GPIO33. ...
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... DUART is ready to send data and requires a clear-to-send signal to initiate transfer. Peripherals drive the DDATA2/CTS0/GPIO3 and DDATA0/CTS1/SDATA0_SDIO1/GPIO1 inputs to indicate to the SCF5250 serial module that it can begin data transmission. Table 7. Timer Module Signals Description The SDATAO1/TOUT0/GPIO18 programmable output pulse or toggle on various timer events. ...
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... Serial Audio Data In Serial Audio Data Out Serial audio error flag Serial audio CFLG SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 16 Table 8. Serial Audio Interface Signals The SCLK1/GPIO20, SCLK2/GPIO22 and SCLK3/GPIO35, multiplexed pins can serve as general purpose I/Os or serial audio bit clocks ...
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... Serial Module Signal Digital Audio In Digital Audio Out 4.13 Subcode Interface There is a 3-line subcode interface on the SCF5250. This 3-line subcode interface allows the device to format and transmit subcode in EIAJ format channel encoder device. The three signals are described in Table 10. ...
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... Table 12. Queued Serial Peripheral Interface (QSPI) Signals Serial Module Signal QSPICLK/SUBR/GPIO25 RCK/QSPIDIN/QSPI_DOUT/GPIO26 RCK/QSPI_DIN/QSPI_DOUT/GPIO26 QSPI_DOUT/SFSY/GPIO27 SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 18 Table 11. Flash Memory Card Signals Clock out for both MemoryStick interfaces and for SecureDigital Secure Digital command line MemoryStick interface 2 data i/o ...
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... The internal PLL generates this PSTCLK/GPIO51 and output signal, and is the processor clock output that is used as the timing reference for the Debug bus timing (DDATA[3:0] and PST[3:0]). The PSTCLK/GPIO51 is at the same frequency as the core processor. SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Description ...
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... Processor Status The processor status pins, PST0/GPIO50, PST1/GPIO49, PST2/INTMON/GPIO48, and PST3/INTMON/GPIO47, indicate the SCF5250 processor status. During debug mode, the timing is synchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer. Table 13 shows the encodings of these signals ...
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... To exit power down mode, apply a LOW level to the WAKE_UP/GPIO21 input pin. 4.23 On-chip Linear Regulator The SCF5250 includes an on-chip linear regulator. This regulator provides an 1.2 V output which is intended to be used to power the SCF5250 core. Three pins are associated with this function. LININ, LINOUT and LINGND. Typically LININ would be fed by the I/O (PAD) supply (3.3 V) with separate filtering recommended to provide some isolation between the I/O and the core ...
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... Table 16. Recommended Operating Supply Voltages Pin Name CORE-VDD CORE-VSS PAD-VDD PAD-VSS ADVDD ADGND OSCPAD-VDD OSCPAD-GND PLLCORE1VDD PLLCORE1GND PLLCORE2VDD PLLCORE2GND LIN SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 22 Table 14. Maximum Ratings (continued) Symbol stg Table 15. Operating Temperature ...
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... A pmos regulator is employed as a current source in this Linear regulator 10µF capacitor (ESR 0 ... 5 Ohm) is needed on the output pin (LINOUT) to integrate the current. Typically this will require the use of a Tantalum type capacitor. SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Symbol Min ...
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... SCL, SDA, PST[3:0], DDATA[3:0], TDSO, SDRAS, SDCAS, SDWE, SD_CS0, SDLDQM, SDUDQM, R/W TOUT0, RTS[1:0], TXD[1:0], SCLK[4:1] BKPT/TMS, DSI/TDI, DSCLK/TRST Capacitance C is periodically sampled rather than 100% tested. IN SCLK[4:1], SCL0, SCL1, SDA0, SDA1, CRIN, RSTI SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 24 Symbol 4mA ...
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... MHz; no other values are allowed. The System Clock is derived from one of these crystals via an internal PLL. CRIN PSTCLK BCLK Signals above are shown in relation to the clock. No relationship between signals is implied or intended. SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Table 19. Clock Timing Specification Characteristic Min 1 5.00 14 ...
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... AC timing specs assume 40pF load capacitance on BCLK and a 50pF load capacitance on output pins. If this value is different, the input and output timing specifications would need to be adjusted to match the clock load. SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 26 Table 20. Input AC Timing Specification Characteristic Table 21 ...
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... SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Figure 3. Input/Output Timing Definition-I Electrical Characteristics 27 ...
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... Electrical Characteristics BCLK INPUTS BCLK OUTPUTS HIZ OUTPUTS SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1 B13 H1 Figure 4. Input/Output Timing Definition-III B4 B14 H2 Freescale Semiconductor ...
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... PSTCLK DSCLK DSI PST[3:0] DDATA[3:0] DSO SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Table 22. Debug AC Timing Specification Characteristic Figure 5. Debug Timing Definition ...
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... T4 BCLK to TOUT Valid (output valid) T5 BCLK to TOUT Invalid (output hold) T6 TIN Pulse Width T7 TOUT Pulse Width BCLK T2 TIN TIN TOUT SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 30 Characteristic Figure 6. Timer Module Timing Definition Units Min Max 3T — bus clocks 6 — ...
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... CTS Valid to BCLK (input setup) U4 BCLK to CTS Invalid (input hold) U5 BCLK to TXD Valid (output valid) U6 BCLK to TXD Invalid (output hold) U7 BCLK to RTS Valid (output valid) U8 BCLK to RTS Invalid (output hold) SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Characteristic BCLK U1 RXD U3 CTS U5 TXD U7 RTS Figure 7 ...
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... Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values. 3. Specified at a nominal 20 pF load. SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 32 Characteristic Characteristic = 2 ...
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... SCL or SDA are actively being driven or held low by the processor. 3. SCL and SDA are internally synchronized.This setup time must be met only if recognition on a particular clock is required. SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Figure 8 ...
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... Table 28. General-Purpose I/O Port AC Timing Specifications Num P1 GPIO Valid to BCLK (input setup) P2 BCLK to GPIO Invalid (input hold) P3 BCLK to GPIO Valid (output valid) P4 BCLK to GPIO Invalid (output hold) SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 34 M10 BCLK M11 M12 Characteristic Min 6 0 — ...
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... TCK falling to TDO Valid (signal from driven or three-state) J10 TCK falling to TDO High Impedance J11 TCK falling to Boundary Scan Data Valid (signal from driven or three-state) SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor BCLK GPIO IN P2 GPIO OUT P4 Characteristic =0 ...
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... Num J12 TCK falling to Boundary Scan Data High Impedance TCK TDI, TMS BOUNDARY SCAN DATA INPUT TRST TDO BOUNDARY SCAN DATA OUTPUT SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 36 Characteristic J1 J2A J2B J11 Figure 11. JTAG Timing Units Min Max — ...
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... Table 31. SCLK OUTPUT, SDATA0 OUTPUT Timing Specifications Name TU TD SCLK (OUTPUT) SDATAO1, 2 (OUTPUT) Figure 13. SCLK Output, SDATAO Output Timing Diagram SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Characteristic TU Characteristic SCLK fall to SDATAO rise SCLK fall to SDATAO fall TU Electrical Characteristics ...
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... DATA16 02 A23/GPO54 03 PAD-VDD 04 A22 05 A21 06 A20/A24 07 A19 08 A18 SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 38 Characteristic TSU Table 33. 144 QFP Pin Assignments Type Description I/O Data I/O SDRAM address / static adr O SDRAM address / static adr O SDRAM address / static adr O SDRAM address / static adr ...
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... CS0/CS4 OSC PAD VDD 34 CRIN SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Type Description O SDRAM address / static adr O SDRAM address / static adr O SDRAM address / static adr O SDRAM address / static adr O SDRAM address / static adr ...
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... GPIO13 50 EBUIN3/CMD_SDIO2/ GPIO14 51 PAD VDD 52 EBUIN1/GPIO36 53 EBUOUT1/GPIO37 54 XTRIM/GPIO0 55 CS1/QSPI_CS3/GPIO28 56 RCK/ QSPI_DIN/QSPI_DOUT/ GPIO26 SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 40 Type Description O Crystal clock output OSC_PAD_GND O Output Enable I/O IDE DIOW I/O IDE interface IORDY I/O IDE interface DIOR I/O External buffer 2 enable I/O External buffer 1 enable ...
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... ADGND 75 ADIN3/GPI55 76 ADIN4/GPI56 77 ADIN5/GPI57 78 ADREF 79 ADOUT/SCLK4/ GPIO58 SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Type Description I/O QSPI clock pin / subcode interface I/O QSPI Data Output / subcode interface SFSY I/O QSPI Chip select 1 output / audio interface EBU output 2 I/O QSPI chip select 0 / ...
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... GPIO47 96 PST2/INTMON2/ GPIO48 97 PAD GND 98 PST1/GPIO49 99 PST0/GPIO50 100 PSTCLK/GPIO51 101 TDO/DSO SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 42 Type Description I/O Audio interface LRCK3 / Audio master clock input I/O Audio interface SCLK3 I/O I2C0 clock line / FlashMedia Data interface I/O I2C0 data / FlashMedia data interface ...
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... PAD VDD 121 SDRAS/GPIO59 122 SD_CS0/GPIO60 123 SDLDQM/GPO52 124 SDUDQM/GPO53 125 BCLKE/GPIO63 126 BCLK/GPIO40 127 DATA31 128 DATA30 SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor Type Description I JTAG/debug I JTAG I JTAG/debug I JTAG/Debug I Reset I/O Audio interfaces serial clock 2 I/O Audio interfaces EBU out 1 ...
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... DATA21 140 DATA20 141 PAD GND 142 DATA19 143 DATA18 144 DATA17 6.2 Package The SCF5250 is assembled in 144-pin QFP package. Thermal characteristics are not available at this time. SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 44 Type Description I/O Data I/O Data I/O Data I/O Data I/O ...
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... THIS PAGE INTENTIONALLY LEFT BLANK SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor 45 ...
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... THIS PAGE INTENTIONALLY LEFT BLANK SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 46 Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor 47 ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2005. All rights reserved. Document Number: SCF5250 Rev. 1.1 04/2005 ...