w77e58 Winbond Electronics Corp America, w77e58 Datasheet - Page 24

• Manufacturer Part Number: w77e58
• Description: 8 Bit Microcontroller
• Manufacturer: Winbond Electronics Corp America

STATUS REGISTER
HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority
LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority
XTUP: Crystal Oscillator Warm-up Status. when set, this bit indicates CPU has detected clock to be
SPTA1: Serial Port 1 Transmit Activity. This bit is set during serial port 1 is currently transmitting
SPRA1: Serial Port 1 Receive Activity. This bit is set during serial port 1 is currently receiving a data.
SPTA0: Serial Port 0 Transmit Activity. This bit is set during serial port 0 is currently transmitting
SPRA0: Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently receiving a data.
TIMED ACCESS
TA: The Timed Access register controls the access to protected bits. To access protected bits, the
user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA.
Now a window is opened in the protected bits for three machine cycles, during which the user
can write to these bits.
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
ready. Each time the crystal oscillator is restarted by exit from power down mode or the XTOFF
bit is set, hardware will clear this bit. This bit is set to 1 after a power-on reset. When this bit is
cleared, it prevents software from setting the XT/ RG bit to enable CPU operation from crystal
oscillator.
data. It is cleared when TI_1 bit is set by hardware. Changing the Clock Divide Control bits
CD0,CD1 will be ignored when this bit is set to 1 and SWB = 1.
It is cleared when RI_1 bit is set by hardware. Changing the Clock Divide Control bits
CD0,CD1 will be ignored when this bit is set to 1 and SWB = 1.
data. It is cleared when TI bit is set by hardware. Changing the Clock Divide Control bits
CD0,CD1 will be ignored when this bit is set to 1 and SWB = 1.
It is cleared when RI bit is set by hardware. Changing the Clock Divide Control bits CD0,CD1
will be ignored when this bit is set to 1 and SWB = 1.
Mnemonic: STATUS
Mnemonic: TA
Bit:
Bit:
7
-
TA.7
7
HIP
6
TA.6
6
LIP
5
TA.5
- 24 -
5
XTUP
4
TA.4
4
SPTA1
Preliminary W77E58
3
TA.3
3
Address: C5h
Address: C7h
SPRA1
TA.2
2
2
SPTA0
TA.1
1
1
SPRA0
TA.0
0
0